Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
16-6
Freescale Semiconductor
XLB Arbiter Registers—MBAR + 0x1F00
16.2.4
Arbiter Interrupt Enable Register (R/W)—MBAR + 0x1F4C
The Arbiter Interrupt Enable Register is used to enable a status bit to cause an interrupt. If the interrupt enable and corresponding status bits
are set in the Arbiter Status Register and the Arbiter Interrupt Enable Register, the arbiter will assert the internal arb_int signal. Normally, an
interrupt service routine would read the status register to determine the state of the arbiter. It is possible that multiple conditions exist that
would cause an interrupt. Disabling an interrupt by writing a 0 to a bit in this register will not clear the status bit in the Arbiter Status Register.
are set in the Arbiter Status Register and the Arbiter Interrupt Enable Register, the arbiter will assert the internal arb_int signal. Normally, an
interrupt service routine would read the status register to determine the state of the arbiter. It is possible that multiple conditions exist that
would cause an interrupt. Disabling an interrupt by writing a 0 to a bit in this register will not clear the status bit in the Arbiter Status Register.
NOTE
For SEAE, ECWE, TTME and ATE interrupt conditions, the arbiter also generates a TEA at a later
time (dependent upon XL bus activity), which will cause a Machine Check exception. As a result,
state information for the interrupted exception in the save/restore registers (SRR0 and SRR1) may be
lost. Therefore, it is recommended that SEA, ECW, TTM, and ATE remain disabled at all times. It is
possible to enable an arbiter interrupt for MME, TTAE, TTRE, as they do not result in a TEA; in case
of DTE and BAE, arbiter interrupt can be enabled, as the TEA assertion always preceeds the interrupt.
time (dependent upon XL bus activity), which will cause a Machine Check exception. As a result,
state information for the interrupted exception in the save/restore registers (SRR0 and SRR1) may be
lost. Therefore, it is recommended that SEA, ECW, TTM, and ATE remain disabled at all times. It is
possible to enable an arbiter interrupt for MME, TTAE, TTRE, as they do not result in a TEA; in case
of DTE and BAE, arbiter interrupt can be enabled, as the TEA assertion always preceeds the interrupt.
Table 16-3. Arbiter Status Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Rsvd
SEA
MM
TTA
TTR
ECW
TTM
BA
DT
AT
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:22
—
Reserved
23
SEA
Slave Error Acknowledge. This bit is set when an error is detected by any slave devices
during the transfer.
during the transfer.
24
MM
Multiple Masters at Priority 0. If more than one master is recognized at priority 0, this bit is
set. Once this occurs, this bit will remain set until cleared. The arbiter recognizes priority
by the hardware-wired mNpri signals or (if enabled) the Arbiter Master N Priority Register.
This bit is intended to help in tuning dynamic priority algorithm development.
set. Once this occurs, this bit will remain set until cleared. The arbiter recognizes priority
by the hardware-wired mNpri signals or (if enabled) the Arbiter Master N Priority Register.
This bit is intended to help in tuning dynamic priority algorithm development.
25
TTA
TT Address Only. The arbiter automatically AACKs for address only TT (transfer type)
codes. This bit is set when this condition occurs.
For a description of TT codes, see the MPC603e Users’ Manual, Section 7.2.
codes. This bit is set when this condition occurs.
For a description of TT codes, see the MPC603e Users’ Manual, Section 7.2.
26
TTR
TT Reserved. The arbiter automatically AACKs for reserved TT (transfer type) codes. This
bit is set when this condition occurs.
For a description of TT codes, see the MPC603e Users’ Manual, Section 7.2.
bit is set when this condition occurs.
For a description of TT codes, see the MPC603e Users’ Manual, Section 7.2.
27
ECW
External Control Word Read/Write. External Control Word Read/Write operations are not
supported on the XLB. If either occur, the arbiter AACKs and TEAs the transaction, and
sets this bit.
supported on the XLB. If either occur, the arbiter AACKs and TEAs the transaction, and
sets this bit.
28
TTM
TBST/TSIZ mismatch. Set when an illegal/reserved TBST and TSIZ[0:2] combinations
occur. These combinations are TBST asserted and TSIZ[0:2] = 000, 001, 011, or 1xx
(where “x” is 0 or 1).
For a description of TBST and TSIZ, see the MPC603e Users’ Manual, Section 7.2.
occur. These combinations are TBST asserted and TSIZ[0:2] = 000, 001, 011, or 1xx
(where “x” is 0 or 1).
For a description of TBST and TSIZ, see the MPC603e Users’ Manual, Section 7.2.
29
BA
Bus Activity Tenure Time-out. Set when the bus activity time-out counter expires.
30
DT
Data Tenure Time-out. Set when the data tenure time-out counter expires.
31
AT
Address Tenure Time-out. Set when the address tenure time-out counter expires.