Freescale Semiconductor MPC5200B ユーザーズマニュアル
XLB Arbiter Registers—MBAR + 0x1F00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
16-7
16.2.5
Arbiter Address Capture Register (R)—MBAR + 0x1F50
The Arbiter Address Capture Register captures the address for a tenure that has either:
•
an address time-out,
•
a data time-out, or
•
a TEA from another source
The captured value is held until unlocked by writing any value to the Arbiter Address Capture Register or Arbiter Bus Signal Capture Register.
This value is also unlocked by writing a 1 to either the Arbiter Status Register, bit 30 (Data Tenure Time-out Status) or bit 31 (Address Tenure
Time-Out Status). Unlocking the register does not clear its contents.
This value is also unlocked by writing a 1 to either the Arbiter Status Register, bit 30 (Data Tenure Time-out Status) or bit 31 (Address Tenure
Time-Out Status). Unlocking the register does not clear its contents.
Table 16-4. Arbiter Interrupt Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Rsvd
SEAE MME
TTAE
TTRE
ECWE
TTME
BAE
DTE
ATE
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:22
—
Reserved
23
SEAE
Slave Error Acknowledge interrupt enable
24
MME
Multiple Masters at priority 0 interrupt enable
25
TTAE
TT Address Only interrupt enable
26
TTRE
TT Reserved interrupt enable
27
ECWE
External Control Word Read/Write interrupt enable
28
TTME
TBST/TSIZ mismatch interrupt enable
29
BAE
Bus Activity Tenure Time-out interrupt enable
30
DTE
Data Tenure Time-out interrupt enable
31
ATE
Address Tenure Time-out interrupt enable
Table 16-5. Arbiter Address Capture Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Address[0:15]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Address[16:31]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0