Freescale Semiconductor MC68HC908MR16 ユーザーズマニュアル
Timer Interface A (TIMA)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
230
Freescale Semiconductor
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA
channel 0 and TIMA channel 2 status and control registers.
channel 0 and TIMA channel 2 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1A pin to
general-purpose I/O.
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TCH3A pin to
general-purpose I/O.
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A
≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHxA pin once PWM,
input capture, or output compare operation is enabled. See
input capture, or output compare operation is enabled. See
. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
the TSTOP and TRST bits in the TIMA status and control register (TASC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E, and pin PTEx/TCHxA
is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits
and becomes transparent to the respective pin when PWM, input capture, or output compare mode is
enabled.
is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits
and becomes transparent to the respective pin when PWM, input capture, or output compare mode is
enabled.
shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin is stable for at least two bus clocks.
sure that the PTEx/TACHx pin is stable for at least two bus clocks.