Motorola CPCI-6020 ユーザーズマニュアル
Local PCI Bus Resources
Functional Description
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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4.3
Local PCI Bus Resources
As stated earlier in this chapter, the CPCI-6020 features two host bridges (provided by Harrier
A and B ASICs), which allow for two independent PCI Bus hierarchies. The resources of these
two buses are described in the following subsections.
A and B ASICs), which allow for two independent PCI Bus hierarchies. The resources of these
two buses are described in the following subsections.
4.3.1
PCI Bus A Resources
The Harrier A ASIC serves as the bridge from the processor bus (marked PowerPC Bus on the
block diagram) to local PCI Bus A. In addition to the Harrier A ASIC, PCI Bus A is connected to
two CompactPCI domains: a local domain using a transparent PCI-to-PCI bridge and the J1
and J2 connectors and a remote domain for connection to a Motorola HA chassis using the J4
connector. PCI Bus A also serves as an interface to the primary Ethernet port on the front panel,
a PCI/ISA bridge connecting ESCC, CIO, and four USB ports. All features on PCI Bus A are
described in the following subsections.
block diagram) to local PCI Bus A. In addition to the Harrier A ASIC, PCI Bus A is connected to
two CompactPCI domains: a local domain using a transparent PCI-to-PCI bridge and the J1
and J2 connectors and a remote domain for connection to a Motorola HA chassis using the J4
connector. PCI Bus A also serves as an interface to the primary Ethernet port on the front panel,
a PCI/ISA bridge connecting ESCC, CIO, and four USB ports. All features on PCI Bus A are
described in the following subsections.
4.3.1.1
Local CompactPCI Bus
PCI Bus A provides a local CompactPCI Bus interface by using the Intel 21154 PCI-to-PCI
bridge chip. This device implements a 64-bit primary data bus and 64-bit secondary data bus
interface and is PCI 2.1 compliant. The 21154 provides read/write data buffering in both
directions.
bridge chip. This device implements a 64-bit primary data bus and 64-bit secondary data bus
interface and is PCI 2.1 compliant. The 21154 provides read/write data buffering in both
directions.
The 21154 supports +3.3 V or +5 V signalling at the PCI busses with a separate VIO pin for the
primary and secondary bus buffers. The primary bus signalling voltage is tied to +5 V. The
secondary bus signalling voltage is tied to the CPCI Bus VIO, so the CPCI-6020 is a universal
board that may operate in a +3.3 V or +5 V chassis.
primary and secondary bus buffers. The primary bus signalling voltage is tied to +5 V. The
secondary bus signalling voltage is tied to the CPCI Bus VIO, so the CPCI-6020 is a universal
board that may operate in a +3.3 V or +5 V chassis.
A CompactPCI Bus interface will support a maximum of seven CompactPCI cards/loads per
segment when operating at 33 MHz. This CompactPCI Bus interface is compliant with the
CompactPCI 2.0 specification as listed in
segment when operating at 33 MHz. This CompactPCI Bus interface is compliant with the
CompactPCI 2.0 specification as listed in
.
4.3.1.2
Remote (Expansion) CompactPCI Bus
PCI Bus A is also routed to the J4 connector. In a Motorola HA chassis this is routed across the
backplane to a bridge card. On the bridge card this bus interfaces to the remote CompactPCI
Bus through a transparent PCI-to-PCI bridge. The interrupts INTA-D# coming from the bridge
card are kept separate from the interrupts INTA-INTD# from sources on the CPCI-6020 even
though they share the same bus segment.
backplane to a bridge card. On the bridge card this bus interfaces to the remote CompactPCI
Bus through a transparent PCI-to-PCI bridge. The interrupts INTA-D# coming from the bridge
card are kept separate from the interrupts INTA-INTD# from sources on the CPCI-6020 even
though they share the same bus segment.
4.3.1.3
Primary Ethernet Channel
The CPCI-6020 uses an Intel GD82551IT Ethernet Controller to implement a primary
10BaseT/100BaseTx Ethernet channel on PCI Bus A. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The standard board configuration provides for a front panel Ethernet connection via an RJ-45
connector. A custom-build option is available for a rear I/O Ethernet by routing the Ethernet
transmit and receive signal pairs to the J5 connector.
10BaseT/100BaseTx Ethernet channel on PCI Bus A. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The standard board configuration provides for a front panel Ethernet connection via an RJ-45
connector. A custom-build option is available for a rear I/O Ethernet by routing the Ethernet
transmit and receive signal pairs to the J5 connector.
This GD82551IT resides on PCI Bus A and always runs at 33 MHz and 64 bits.