Motorola CPCI-6020 ユーザーズマニュアル

The clock input to the Z85230 PCLK pin is a 10 MHz clock. The two ports will support data 
transfers up to 2.5 Mbs/sec. The Z85230 supplies an interrupt vector during a pseudo interrupt 
acknowledge cycle. The vector is modified based upon the interrupt source within the Z85230.

All modem control lines from the ESCC are multiplexed/de-multiplexed through J3 by the P2MX 
function due to I/O pin limitations.

The NEC uPD720101 device provides five USB ports (only four are used) for connectivity with 
any USB compliant device or hub. It is an USB2.0 host controller, having one EHCI (Enhanced 
Host Controller Interface) and two OHCI (Open Host Controller Interface) integrated onto a 
single chip. It is a +3.3 V / +5 V device and supports PCI specification Rev.2.2 (32-bit, 33 MHz). 
This device supports USB2.0 specification and is also backward compatible with USB1.1 
specification. Hi-speed, full-speed or low-speed peripherals are supported along with all of the 
USB transfer types: control, interrupt, bulk, or isochronous.

Two ports are routed to standard USB Series A receptacle at the front panel. The other two 
ports are routed to J5 User I/O connector.

The four ports may be independently powered on and off through the use of an external USB 
power control switch provided on board. Legacy keyboard and mouse interrupts from this 
device are not supported on the CPCI-6020.

The Harrier B ASIC bridges from the processor bus to PCI Bus B. Other than the Harrier, there 
are only two resources on the bus; the secondary Ethernet controller and a PMC slot. The PMC 
slot includes secondary arbitration and IDSEL signals as defined in the VITA 32-199x Processor 
PMC Standard which allows for two possible devices on the PMC on this bus segment. PCI Bus 
B is compliant to PCI Revision 2.1, including 64-bit expansion signals. It runs at +3.3 V levels 
but is tolerant of +5 V signalling from the PMC. This bus runs at 33 MHz unless a 66 MHz 
capable PMC is installed in which case the ethernet controller is disabled and the bus runs at 
66 MHz.

The CPCI-6020 contains four EIA-E700 AAAB connectors which provide a 32/64-bit PCI 
interface to an IEEE P1386.1 compliant PMC. Connectors J11-J13 provide the 32/64-bit PCI 
interface while J14 provides a user I/O path from the PMC slot to the CompactPCI backplane. 
PMC user I/O signals are routed from the PMC J14 connector to the CompactPCI J3 connector 
following the PIM differential signalling recommendations. A cutout in the CPCI-6020 allows for 
front I/O through the PMC face plate.

If a 66 MHz capable PMC is installed, which is indicated by the state of its M66EN pin, PCI Bus 
B is also configured at power up to run at 66 MHz. In this case, the 82551IT Ethernet device on 
this bus, which is not 66 MHz capable, is disabled. If no PMC is installed, or if the PMC is not 
66 MHz capable, then the bus runs at 33 MHz and the Ethernet device remains enabled. A 
jumper is provided to override the M66EN pin from the PMC and force the bus to run at 33 MHz.