Motorola CPCI-6020 ユーザーズマニュアル
Local CompactPCI Bus Interface
Functional Description
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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The PCI Bus routed to the J4 connector provides the communication path to the local bridge
card. There are also four signals in the J3 connector which comprise the communication with
the remote bridge card. When the CPCI-6020 is in control of the local CompactPCI Bus, these
signals allow the HSC on the remote bridge card to force the CPCI-6020 to quiesce the local
CompactPCI Bus and tri-state its 21154. This allows that HSC to then activate its own 21154
and assume control of the local CompactPCI Bus.
card. There are also four signals in the J3 connector which comprise the communication with
the remote bridge card. When the CPCI-6020 is in control of the local CompactPCI Bus, these
signals allow the HSC on the remote bridge card to force the CPCI-6020 to quiesce the local
CompactPCI Bus and tri-state its 21154. This allows that HSC to then activate its own 21154
and assume control of the local CompactPCI Bus.
4.12.2
Local CompactPCI Bus Interface
Backplane communication is accomplished through the Intel 21154 transparent PCI-to-PCI
bridge. This device is not intended to support hot swap circuitry which has been added to the
CPCI-6020 to adapt the 21154 to this purpose and is described in the following sections.
bridge. This device is not intended to support hot swap circuitry which has been added to the
CPCI-6020 to adapt the 21154 to this purpose and is described in the following sections.
4.12.3
Secondary Bus Arbitration
The 21154 internal secondary bus arbiter is not used on the CPCI-6020 because special HA
features are required. An external arbiter is used instead.
features are required. An external arbiter is used instead.
The external arbiter includes an interface to the Hot Swap Controller (HSC) located on the
remote bridge board. Through this interface the HSC may cause the arbiter to refuse to grant
the local CompactPCI Bus to any of the peripheral slot boards. In this manner the bus may be
made quiescent in preparation for a transfer of control from the CPCI-6020 to the bridge board
that bridges the remote domain down to the local CompactPCI Bus.
remote bridge board. Through this interface the HSC may cause the arbiter to refuse to grant
the local CompactPCI Bus to any of the peripheral slot boards. In this manner the bus may be
made quiescent in preparation for a transfer of control from the CPCI-6020 to the bridge board
that bridges the remote domain down to the local CompactPCI Bus.
4.12.4
Secondary Bus Tri-Stating
When the CPCI-6020 is taken offline by the bridge board from the remote domain, its 21154
must be disabled to prevent it from responding to backplane transactions. The 21154 is
designed to drive its secondary bus signals to an inactive state when in reset. This would
prevent the remote bridge from assuming control of this bus. To overcome this there is a device
on the CPCI-6020 which can use the JTAG interface on the 21154 to put it into a high
impedance mode. That device is controlled by the remote bridge card.
must be disabled to prevent it from responding to backplane transactions. The 21154 is
designed to drive its secondary bus signals to an inactive state when in reset. This would
prevent the remote bridge from assuming control of this bus. To overcome this there is a device
on the CPCI-6020 which can use the JTAG interface on the 21154 to put it into a high
impedance mode. That device is controlled by the remote bridge card.
4.12.5
System Slot Hot Swap
The CPCI-6020 may be safely inserted and extracted from the system chassis while power is
applied. Hot swap circuitry protects the board from electrical damage.
applied. Hot swap circuitry protects the board from electrical damage.
In systems that support high availability, the CompactPCI Bus may be active while the CPCI-
6020 is inserted and/or removed without disturbing the bus traffic. This is accomplished by pin-
staged CompactPCI Bus connections, a switched pre-charged voltage level applied to bussed
pins and tri-stating of PCI-to-PCI bridge signals during insertion and removal.
6020 is inserted and/or removed without disturbing the bus traffic. This is accomplished by pin-
staged CompactPCI Bus connections, a switched pre-charged voltage level applied to bussed
pins and tri-stating of PCI-to-PCI bridge signals during insertion and removal.
The BD_SEL# signal from CompactPCI Bus J1 pin D15 must be driven true (low) for the back
end power supplies to switch on. When BD_SEL# is not asserted only a small portion of the
CPCI-6020 circuitry is powered.
end power supplies to switch on. When BD_SEL# is not asserted only a small portion of the
CPCI-6020 circuitry is powered.