Cypress CY7C602xx ユーザーズマニュアル
CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E
Page 63 of 68
Figure 20-6. SPI Slave Timing, CPHA = 0
1
MSB
T
SSU
LSB
T
SHD
T
SCKH
T
SDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
T
SCKL
T
SDO
LSB
MSB
T
SSS
T
SSH
21. Ordering Information
Ordering Code
FLASH Size
RAM Size
Package Type
CY7C60123-PVXC
8K
256
48-SSOP
CY7C60123-PXC
8K
256
40-PDIP
CY7C60113-PVXC
8K
256
28-SSOP
CY7C60223-PXC
8K
256
24-PDIP
CY7C60223-SXC
8K
256
24-SOIC
CY7C60223-QXC
8K
256
24-QSOP
22. Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may
degrade device reliability.
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may
degrade device reliability.
Parameter
Description
Min
Typical
Max
Unit
T
BAKETEMP
Bake Temperature
125
See package label
°C
T
BAKETIME
Bake Time
See package label
72
hours