Cypress CY7C602xx マニュアル

目次

• 1. Features

  1
• 2. Logic Block Diagram

  1
• 3. Applications

  2
• 4. Introduction

  2
• 5. Conventions

  2
• 6. Pinouts

  3
  • 6.1 Pin Assignments

    4
• 7. Register Summary

  6
• 8. CPU Architecture

  8
• 9. CPU Registers

  8
  • 9.1 Flags Register

    8
    • 9.1.1 Accumulator Register

      9
    • 9.1.2 Index Register

      9
    • 9.1.3 Stack Pointer Register

      9
    • 9.1.4 CPU Program Counter High Register

      9
    • 9.1.5 CPU Program Counter Low Register

      9
  • 9.2 Addressing Modes

    10
    • 9.2.1 Source Immediate

      10
    • 9.2.2 Source Direct

      10
    • 9.2.3 Source Indexed

      10
    • 9.2.4 Destination Direct

      10
    • 9.2.5 Destination Indexed

      11
    • 9.2.6 Destination Direct Source Immediate

      11
    • 9.2.7 Destination Indexed Source Immediate

      11
    • 9.2.8 Destination Direct Source Direct

      11
    • 9.2.9 Source Indirect Post Increment

      12
    • 9.2.10 Destination Indirect Post Increment

      12
• 10. Instruction Set Summary

  12
• 11. Memory Organization

  14
  • 11.1 Flash Program Memory Organization

    14
  • 11.2 Data Memory Organization

    15
  • 11.3 Flash

    15
    • 11.3.1 Flash Programming and Security

      15
    • 11.3.2 In-System Programming

      15
  • 11.4 SROM

    15
    • 11.4.1 Return Codes

      16
  • 11.5 SROM Function Descriptions

    16
    • 11.5.1 SWBootReset Function

      16
    • 11.5.2 ReadBlock Function

      16
    • 11.5.3 WriteBlock Function

      17
    • 11.5.4 EraseBlock Function

      17
    • 11.5.5 ProtectBlock Function

      17
    • 11.5.6 EraseAll Function

      18
    • 11.5.7 TableRead Function

      18
  • 11.6 SROM Table Read Description

    19
    • 11.6.1 Checksum Function

      20
• 12. Clocking

  21
  • 12.1 Trim Values for the IOSCTR Register

    21
  • 12.2 Clock Architecture Description

    22
    • 12.2.1 CPU Clock

      22
    • 12.2.2 Interval Timer Clock (ITMRCLK)

      25
    • 12.2.3 Timer Capture Clock (TCAPCLK)

      26
    • 12.2.4 Internal Clock Trim

      28
    • 12.2.5 External Clock Trim

      28
    • 12.2.6 LPOSC Trim

      29
  • 12.3 CPU Clock During Sleep Mode

    29
• 13. Reset

  30
  • 13.1 Power On Reset

    31
  • 13.2 Watchdog Timer Reset

    31
• 14. Sleep Mode

  31
  • 14.1 Sleep Sequence

    32
    • 14.1.1 Low Power in Sleep Mode

      32
  • 14.2 Wakeup Sequence

    33
• 15. Low Voltage Detect Control

  34
  • 15.1 POR Compare State

    35
  • 15.2 ECO Trim Register

    35
• 16. General Purpose IO Ports

  36
  • 16.1 Port Data Registers

    36
    • 16.1.1 P0 Data

      36
    • 16.1.2 P1 Data

      36
    • 16.1.3 P2 Data

      37
    • 16.1.4 P3 Data

      37
    • 16.1.5 P4 Data

      37
  • 16.2 GPIO Port Configuration

    37
    • 16.2.1 Int Enable

      37
    • 16.2.2 Int Act Low

      37
    • 16.2.3 TTL Thresh

      37
    • 16.2.4 High Sink

      38
    • 16.2.5 Open Drain

      38
    • 16.2.6 Pull Up Enable

      38
    • 16.2.7 Output Enable

      38
    • 16.2.8 SPI Use

      38
    • 16.2.9 P0.0/CLKIN Configuration

      38
    • 16.2.10 P0.1/CLKOUT Configuration

      39
    • 16.2.11 P0.2/INT0-P0.4/INT2 Configuration

      39
    • 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration

      40
    • 16.2.13 P0.7 Configuration

      40
    • 16.2.14 P1.0 Configuration

      40
    • 16.2.15 P1.1 Configuration

      41
    • 16.2.16 P1.2 Configuration

      41
    • 16.2.17 P1.3 Configuration (SSEL)

      41
    • 16.2.18 P1.4-P1.6 Configuration (SCLK, SMOSI, SMISO)

      42
    • 16.2.19 P1.7 Configuration

      42
    • 16.2.20 P2 Configuration

      42
    • 16.2.21 P3 Configuration

      43
    • 16.2.22 P4 Configuration

      43
• 17. Serial Peripheral Interface (SPI)

  44
  • 17.1 SPI Data Register

    45
  • 17.2 SPI Configure Register

    45
  • 17.3 SPI Interface Pins

    47
• 18. Timer Registers

  47
  • 18.1 Registers

    47
    • 18.1.1 Free Running Counter

      47
    • 18.1.2 Time Capture

      48
    • 18.1.3 Programmable Interval Timer

      50
• 19. Interrupt Controller

  54
  • 19.1 Architectural Description

    54
  • 19.2 Interrupt Processing

    55
  • 19.3 Interrupt Latency

    55
  • 19.4 Interrupt Registers

    55
    • 19.4.1 Interrupt Clear Register

      55
    • 19.4.2 Interrupt Mask Registers

      56
    • 19.4.3 Interrupt Vector Clear Register

      58
• 20. Absolute Maximum Ratings

  59
  • 20.1 DC Characteristics

    59
  • 20.2 AC Characteristics

    60
• 21. Ordering Information

  63
• 22. Package Handling

  63
• 23. Package Diagrams

  64
• 24. Document History Page

  67
• Sales, Solutions, and Legal Information

  68
  • Worldwide Sales and Design Support

    68
  • Products

    68
  • PSoC Solutions

    68