Cypress CY7C638xx ユーザーズマニュアル
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K
Page 31 of 83
13. Low Voltage Detect Control
Table 13-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
PORLEV[1:0]
Reserved
VM[2:0]
Read/Write
–
–
R/W
R/W
–
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register controls the configuration of the Power on Reset/Low voltage Detection block.
Note
Note
This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
Bit [7:6]:
Reserved
Bit [5:4]:
PORLEV[1:0]
This field controls the level below which the precision power on reset (PPOR) detector generates a reset.
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = 5V Range, >4.75V (trip near 4.65V). This setting must be used when operating the CPU above 12 MHz.
1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = 5V Range, >4.75V (trip near 4.65V). This setting must be used when operating the CPU above 12 MHz.
1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (
internal PPOR comparator state with trip point set to the 3V range setting.
Bit 3:
Reserved
Bit [2:0]:
VM[2:0]
VM[2:0]
LVD Trip
Point (V) Min
LVD Trip
Point (V) Typ
LVD Trip
Point (V) Max
000
Reserved
Reserved
Reserved
001
Reserved
Reserved
Reserved
010
Reserved
Reserved
Reserved
011
Reserved
Reserved
Reserved
100
4.439
4.48
4.528
101
4.597
4.64
4.689
110
4.680
4.73
4.774
111
4.766
4.82
4.862