Cypress CY7C638xx マニュアル

目次

• 1. Features

  1
  • 1.1 Applications

    1
• 2. Logic Block Diagram

  2
• 3. Introduction

  3
• 4. Conventions

  3
• 5. Pinouts

  4
• 6. CPU Architecture

  7
• 7. CPU Registers

  8
  • 7.1 Flags Register

    8
  • 7.2 Addressing Modes

    9
    • 7.2.1 Source Immediate

      9
    • 7.2.2 Source Direct

      10
    • 7.2.3 Source Indexed

      10
    • 7.2.4 Destination Direct

      10
    • 7.2.5 Destination Indexed

      10
    • 7.2.6 Destination Direct Source Immediate

      11
    • 7.2.7 Destination Indexed Source Immediate

      11
    • 7.2.8 Destination Direct Source Direct

      11
    • 7.2.9 Source Indirect Post Increment

      11
    • 7.2.10 Destination Indirect Post Increment

      11
• 8. Instruction Set Summary

  12
• 9. Memory Organization

  13
  • 9.1 Flash Program Memory Organization

    13
  • 9.2 Data Memory Organization

    14
  • 9.3 Flash

    14
    • 9.3.1 Flash Programming and Security

      14
    • 9.3.2 In System Programming

      14
  • 9.4 SROM

    14
    • 9.4.1 Return Codes

      15
  • 9.5 SROM Function Descriptions

    15
    • 9.5.1 SWBootReset Function

      15
    • 9.5.2 ReadBlock Function

      15
    • 9.5.3 WriteBlock Function

      16
    • 9.5.4 EraseBlock Function

      16
    • 9.5.5 ProtectBlock Function

      16
    • 9.5.6 EraseAll Function

      17
    • 9.5.7 TableRead Function

      17
    • 9.5.8 Checksum Function

      19
• 10. Clocking

  19
  • 10.1 Clock Architecture Description

    21
    • 10.1.1 Interval Timer Clock (ITMRCLK)

      25
    • 10.1.2 Timer Capture Clock (TCAPCLK)

      25
  • 10.2 CPU Clock During Sleep Mode

    26
• 11. Reset

  27
  • 11.1 Power on Reset

    28
  • 11.2 Watchdog Timer Reset

    28
• 12. Sleep Mode

  28
  • 12.1 Sleep Sequence

    29
  • 12.2 Wake up Sequence

    29
  • 12.3 Low Power in Sleep Mode

    30
• 13. Low Voltage Detect Control

  31
  • 13.0.1 ECO Trim Register

    32
• 14. General Purpose IO (GPIO) Ports

  33
  • 14.1 Port Data Registers

    33
  • 14.2 GPIO Port Configuration

    35
    • 14.2.1 Int Enable

      35
    • 14.2.2 Int Act Low

      35
    • 14.2.3 TTL Thresh

      35
    • 14.2.4 High Sink

      35
    • 14.2.5 Open Drain

      35
    • 14.2.6 Pull up Enable

      35
    • 14.2.7 Output Enable

      35
    • 14.2.8 VREG Output/SPI Use

      35
    • 14.2.9 3.3V Drive

      35
• 15. Serial Peripheral Interface (SPI)

  40
  • 15.1 SPI Data Register

    40
  • 15.2 SPI Configure Register

    41
  • 15.3 SPI Interface Pins

    42
• 16. Timer Registers

  43
  • 16.1 Registers

    43
    • 16.1.1 Free Running Counter

      43
    • 16.1.2 Timer Capture

      46
• 17. Interrupt Controller

  50
  • 17.1 Architectural Description

    50
  • 17.2 Interrupt Processing

    51
  • 17.3 Interrupt Trigger Conditions

    51
  • 17.4 Interrupt Latency

    51
  • 17.5 Interrupt Registers

    52
    • 17.5.1 Interrupt Mask Registers

      52
• 18. Regulator Output

  56
  • 18.1 VREG Control

    56
• 19. USB/PS2 Transceiver

  57
  • 19.1 USB Transceiver Configuration

    57
• 20. USB Serial Interface Engine (SIE)

  57
• 21. USB Device

  58
  • 21.1 USB Device Address

    58
  • 21.2 Endpoint 0, 1, and 2 Count

    58
  • 21.3 Endpoint 0 Mode

    59
  • 21.4 Endpoint 1 and 2 Mode

    60
• 22. USB Mode Tables

  61
  • 22.1 Mode Column

    61
  • 22.2 Encoding Column

    61
  • 22.3 SETUP, IN, and OUT Columns

    62
• 23. Details of Mode for Differing Traffic Conditions

  62
• 24. Register Summary

  64
• 25. Voltage Vs CPU Frequency Characteristics

  67
• 26. Absolute Maximum Ratings

  68
• 27. DC Characteristics

  68
• 28. AC Characteristics

  69
• 29. Ordering Information

  75
• 30. Package Handling

  75
• 31. Package Diagrams

  76
• 32. Document History Page

  80
• 33. Sales, Solutions, and Legal Information

  83
  • Worldwide Sales and Design Support

    83
  • Products

    83
  • PSoC Solutions

    83