Cypress CY7C638xx ユーザーズマニュアル

Document 38-08035 Rev. *K

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The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XIO bit in the CPU Flags register

must be set/cleared to select between the two register banks 

The Flags Register is set or reset only with logical instruction.

Reserved

XIO

Super

Carry

Zero

Global IE

–

–

–

R/W

R

RW

RW

RW

0

0

0

0

0

0

1

0

 Reserved

 XIO 

Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1

Super 

Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)
0 = User Code
1 = Supervisor Code

 Carry

Set by the CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry

 Zero

Set by the CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero

 Global IE

Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled

 CPU_F register is only readable with the explicit register address 0xF7. The OR F, expr and AND F, expr instructions must 

be used to set and clear the CPU_F bits.

CPU Accumulator [7:0]

–

–

–

–

–

–

–

–

0

0

0

0

0

0

0

0

 CPU Accumulator [7:0]

8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode