Cypress CY7C63310 ユーザーズマニュアル

Document 38-08035 Rev. *K

Page 32 of 83

Reserved

LVD

PPOR

–

–

–

–

–

–

R

R

0

0

0

0

0

0

0

0

This read only register allows reading the current state of the Low-Voltage-Detection and Precision-Power-On-Reset compar-

ators

 Reserved

 LVD

This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below 

the trip point set by VM[2:0] (See 

)

0 = No low-voltage-detect event
1 = A low-voltage-detect has tripped
Bit 0:

 PPOR

This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below 

the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-power-on-reset event has occurred
Note 

This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.

Sleep Duty Cycle [1:0]

Reserved

R/W

R/W

–

–

–

–

–

–

0

0

0

0

0

0

0

0

This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection 

circuit.

 Sleep Duty Cycle [1:0]

0 0 = 1/128 periods of the Internal 32 kHz Low-speed Oscillator
0 1 = 1/512 periods of the Internal 32 kHz Low-speed Oscillator
1 0 = 1/32 periods of the Internal 32 kHz Low-speed Oscillator
1 1 = 1/8 periods of the Internal 32 kHz Low-speed Oscillator
Note 

This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.