ユーザーズマニュアル目次1. Features11.1 Applications12. Logic Block Diagram23. Introduction34. Conventions35. Pinouts46. CPU Architecture77. CPU Registers87.1 Flags Register87.2 Addressing Modes97.2.1 Source Immediate97.2.2 Source Direct107.2.3 Source Indexed107.2.4 Destination Direct107.2.5 Destination Indexed107.2.6 Destination Direct Source Immediate117.2.7 Destination Indexed Source Immediate117.2.8 Destination Direct Source Direct117.2.9 Source Indirect Post Increment117.2.10 Destination Indirect Post Increment118. Instruction Set Summary129. Memory Organization139.1 Flash Program Memory Organization139.2 Data Memory Organization149.3 Flash149.3.1 Flash Programming and Security149.3.2 In System Programming149.4 SROM149.4.1 Return Codes159.5 SROM Function Descriptions159.5.1 SWBootReset Function159.5.2 ReadBlock Function159.5.3 WriteBlock Function169.5.4 EraseBlock Function169.5.5 ProtectBlock Function169.5.6 EraseAll Function179.5.7 TableRead Function179.5.8 Checksum Function1910. Clocking1910.1 Clock Architecture Description2110.1.1 Interval Timer Clock (ITMRCLK)2510.1.2 Timer Capture Clock (TCAPCLK)2510.2 CPU Clock During Sleep Mode2611. Reset2711.1 Power on Reset2811.2 Watchdog Timer Reset2812. Sleep Mode2812.1 Sleep Sequence2912.2 Wake up Sequence2912.3 Low Power in Sleep Mode3013. Low Voltage Detect Control3113.0.1 ECO Trim Register3214. General Purpose IO (GPIO) Ports3314.1 Port Data Registers3314.2 GPIO Port Configuration3514.2.1 Int Enable3514.2.2 Int Act Low3514.2.3 TTL Thresh3514.2.4 High Sink3514.2.5 Open Drain3514.2.6 Pull up Enable3514.2.7 Output Enable3514.2.8 VREG Output/SPI Use3514.2.9 3.3V Drive3515. Serial Peripheral Interface (SPI)4015.1 SPI Data Register4015.2 SPI Configure Register4115.3 SPI Interface Pins4216. Timer Registers4316.1 Registers4316.1.1 Free Running Counter4316.1.2 Timer Capture4617. Interrupt Controller5017.1 Architectural Description5017.2 Interrupt Processing5117.3 Interrupt Trigger Conditions5117.4 Interrupt Latency5117.5 Interrupt Registers5217.5.1 Interrupt Mask Registers5218. Regulator Output5618.1 VREG Control5619. USB/PS2 Transceiver5719.1 USB Transceiver Configuration5720. USB Serial Interface Engine (SIE)5721. USB Device5821.1 USB Device Address5821.2 Endpoint 0, 1, and 2 Count5821.3 Endpoint 0 Mode5921.4 Endpoint 1 and 2 Mode6022. USB Mode Tables6122.1 Mode Column6122.2 Encoding Column6122.3 SETUP, IN, and OUT Columns6223. Details of Mode for Differing Traffic Conditions6224. Register Summary6425. Voltage Vs CPU Frequency Characteristics6726. Absolute Maximum Ratings6827. DC Characteristics6828. AC Characteristics6929. Ordering Information7530. Package Handling7531. Package Diagrams7632. Document History Page8033. Sales, Solutions, and Legal Information83Worldwide Sales and Design Support83Products83PSoC Solutions83サイズ: 1.77MBページ数: 83Language: Englishマニュアルを開く