Cypress CY7C63310 ユーザーズマニュアル
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K
Page 50 of 83
17. Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the enCoRe II devices. The registers
associated with the interrupt controller allow disabling interrupts
globally or individually. The registers also provide a mechanism
by which a user may clear all pending and posted interrupts, or
clear individual posted or pending interrupts.
The following table lists all interrupts and the priorities that are
The following table lists all interrupts and the priorities that are
available in the enCoRe II devices.
17.1 Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in
on page 51 clocking in a ‘1’.
The interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It prevents a posted
interrupt from becoming pending.
Nested interrupts are accomplished by re-enabling interrupts
Nested interrupts are accomplished by re-enabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
A block diagram of the enCoRe II Interrupt Controller is shown in
A block diagram of the enCoRe II Interrupt Controller is shown in
Table 17-1. Interrupt Numbers, Priorities, Vectors
Interrupt
Priority
Interrupt
Address
Name
0
0000h
Reset
1
0004h
POR/LVD
2
0008h
INT0
3
000Ch
SPI Transmitter Empty
4
0010h
SPI Receiver Full
5
0014h
GPIO Port 0
6
0018h
GPIO Port 1
7
001Ch
INT1
8
0020h
EP0
9
0024h
EP1
10
0028h
EP2
11
002Ch
USB Reset
12
0030h
USB Active
13
0034h
1 mS Interval timer
14
0038h
Programmable Interval Timer
15
003Ch
Timer Capture 0
16
0040h
Timer Capture 1
17
0044h
16-bit Free Running Timer Wrap
18
0048h
INT2
19
004Ch
PS2 Data Low
20
0050h
GPIO Port 2
21
0054h
GPIO Port 3
22
0058h
Reserved
23
005Ch
Reserved
24
0060h
Reserved
25
0064h
Sleep Timer