Freescale Semiconductor MCF52210 ユーザーズマニュアル
Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-12
Freescale Semiconductor
28.4.5
Trigger Definition Register (TDR)
The TDR configures the operation of the hardware breakpoint logic corresponding with the
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug
module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured
as a one- or two-level trigger. TDR[31–16] bits define second-level trigger, and bits 15–0 define first-level
trigger.
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug
module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured
as a one- or two-level trigger. TDR[31–16] bits define second-level trigger, and bits 15–0 define first-level
trigger.
NOTE
The debug module has no hardware interlocks to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded. Disable
TDR (by clearing TDR[29,13]) before defining triggers.
breakpoint triggers while the breakpoint registers are being loaded. Disable
TDR (by clearing TDR[29,13]) before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WDMREG command.
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WDMREG command.
4–3
TT
Transfer Type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates
an external or DMA access (for backward compatibility). These bits affect the TM bits.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates
an external or DMA access (for backward compatibility). These bits affect the TM bits.
2–0
TM
Transfer Modifier. Compared with the local bus transfer modifier signals, which give supplemental information
for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
Table 28-8. AATR Field Descriptions (continued)
Field
Description
TM
TT=00
(normal mode)
TT=10
(emulator mode)
TT=11
(acknowledge/CPU
space transfers)
000
Reserved
Reserved
CPU space access
001
User data access
Reserved
Interrupt ack level 1
010
User code access
Reserved
Interrupt ack level 2
011
Reserved
Reserved
Interrupt ack level 3
100
Reserved
Reserved
Interrupt ack level 4
101
Supervisor data access
Emulator mode access
Interrupt ack level 5
110
Supervisor code access
Emulator code access
Interrupt ack level 6
111
Reserved
Reserved
Interrupt ack level 7