Freescale Semiconductor MCF52210 ユーザーズマニュアル
Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-14
Freescale Semiconductor
20–18
L2EA
Enable Level 2 Address Breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the breakpoint.
three bits disables the breakpoint.
17
L2EPC
Enable Level 2 Pc Breakpoint.
0 Disable PC breakpoint
1 Enable PC breakpoint where the trigger is defined by the logical summation of:
0 Disable PC breakpoint
1 Enable PC breakpoint where the trigger is defined by the logical summation of:
(PBR0 & PBMR) | PBR1 | PBR2 | PBR3
Eqn. 28-1
16
L2PCI
Level 2 PC Breakpoint Invert.
0 The PC breakpoint is defined within the region defined by PBRn and PBMR.
1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.
0 The PC breakpoint is defined within the region defined by PBRn and PBMR.
1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.
15
L2T
Level 2 Trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &
Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 2 trigger = PC_condition & Address_range & Data_condition
1 Level 2 trigger = PC_condition | (Address_range & Data_condition)
Note: Debug Rev A only had the AND condition available for the triggers.
Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 2 trigger = PC_condition & Address_range & Data_condition
1 Level 2 trigger = PC_condition | (Address_range & Data_condition)
Note: Debug Rev A only had the AND condition available for the triggers.
14
L1T
Level 1 Trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &
Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 1 trigger = PC_condition & Address_range & Data_condition
1 Level 1 trigger = PC_condition | (Address_range & Data_condition)
Note: Debug Rev A only had the AND condition available for the triggers.
Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 1 trigger = PC_condition & Address_range & Data_condition
1 Level 1 trigger = PC_condition | (Address_range & Data_condition)
Note: Debug Rev A only had the AND condition available for the triggers.
13
L1EBL
Enable Level 1 Breakpoint. Global enable for the breakpoint trigger.
0 Disables all level 1 breakpoints
1 Enables all level 1 breakpoint triggers
0 Disables all level 1 breakpoints
1 Enables all level 1 breakpoint triggers
Table 28-9. TDR Field Descriptions (continued)
Field
Description
TDR Bit
Description
20
Address breakpoint inverted. Breakpoint is based outside the
range between ABLR and ABHR.
range between ABLR and ABHR.
19
Address breakpoint range. The breakpoint is based on the
inclusive range defined by ABLR and ABHR.
inclusive range defined by ABLR and ABHR.
18
Address breakpoint low. The breakpoint is based on the
address in the ABLR.
address in the ABLR.