Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
113 of 792
NXP Semiconductors
UM10237
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
3.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ.
that are enabled and classified as IRQ.
3.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
3.9 Vector Address Registers 0-31 (VICVectAddr0-31 - 0xFFFF F100 to
17C)
These are read/write accessible registers. These registers hold the addresses of the
Interrupt Service routines (ISRs) for the 32 vectored IRQ slots.
Interrupt Service routines (ISRs) for the 32 vectored IRQ slots.
Table 108. Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description
Bit
Symbol
Value Description
Reset
value
value
31:0
See
0
The interrupt request with this bit number is assigned to the
IRQ category.
IRQ category.
0
1
The interrupt request with this bit number is assigned to the
FIQ category.
FIQ category.
Table 109. IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description
Bit
Symbol
Description
Reset
value
value
31:0 See
.
A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted
enabled, classified as IRQ, and asserted
0
Table 110. FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description
Bit
Symbol
Description
Reset
value
value
31:0 See
.
A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted
enabled, classified as IRQ, and asserted
0