Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
115 of 792
NXP Semiconductors
UM10237
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
3.13 Protection Enable Register (VICProtection - 0xFFFF F020)
This is a read/write accessible register. This one bit register controls access to the VIC
registers by software running in User mode. The VICProtection register itself can only be
accessed in privileged mode.
registers by software running in User mode. The VICProtection register itself can only be
accessed in privileged mode.
4.
Interrupt sources
lists the interrupt sources for each peripheral function. Each peripheral
device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line
may represent more than one interrupt source. There is no significance or priority about
what line is connected where, except for certain standards from ARM.
may represent more than one interrupt source. There is no significance or priority about
what line is connected where, except for certain standards from ARM.
Table 114. Software Priority Mask register (VICSWPriorityMask - address 0xFFFF F024) bit
description
Bit
Symbol
Value Description
Reset
value
value
15:0
VICSWPriorityMask 0
Interrupt priority level is masked.
0xFFFF
1
Interrupt priority level is not masked.
31:16 -
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
reserved bits. The value read from a reserved bit is
not defined.
NA
Table 115. Protection Enable register (VICProtection - address 0xFFFF F020) bit description
Bit
Symbol
Value Description
Reset
value
value
0
VIC_access
0
VIC registers can be accessed in User or privileged mode.
0
1
The VIC registers can only be accessed in privileged mode.
31:1 -
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 116. Connection of interrupt sources to the Vectored Interrupt Controller
Block
Flag(s)
VIC Channel # and
Hex Mask
Hex Mask
WDT
Watchdog Interrupt (WDINT)
0
0x0000 0001
-
Reserved for Software Interrupts only
1
0x0000 0002
ARM Core
Embedded ICE, DbgCommRx
2
0x0000 0004
ARM Core
Embedded ICE, DbgCommTX
3
0x0000 0008
TIMER0
Match 0 - 1 (MR0, MR1)
Capture 0 - 1 (CR0, CR1)
4
0x0000 0010
TIMER1
Match 0 - 2 (MR0, MR1, MR2)
Capture 0 - 1 (CR0, CR1)
5
0x0000 0020
UART0
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
6
0x0000 0040