Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
318 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color0 maps through CRSR_PAL0.
cursor. Color0 maps through CRSR_PAL0.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL0 register are described in
7.20 Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C)
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color1 maps through CRSR_PAL1.
cursor. Color1 maps through CRSR_PAL1.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL1 register are described in
Table 277. Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04)
Bits
Function
Description
Reset
value
value
31:2
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
1
FrameSync
Cursor frame synchronization type.
0 = Cursor coordinates are asynchronous.
1 = Cursor coordinates are synchronized to the frame
synchronization pulse.
synchronization pulse.
0x0
0
CrsrSize
Cursor size selection.
0 = 32x32 pixel cursor. Allows for 4 defined cursors.
1 = 64x64 pixel cursor.
0x0
Table 278. Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)
Bits
Function
Description
Reset
value
value
31:24
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
23:16
Blue
Blue color component.
0x0
15:8
Green
Green color component
0x0
7:0
Red
Red color component
0x0