Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

Once data has been received or sent, the endpoint buffer can be read or written. How this 
is accomplished depends on the endpoint’s type and operating mode. The two operating 
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. 

In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the 
Register Interface. See 

 for a detailed description of 

this mode.

In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See 

 for a detailed description of this mode.

The device controller can access two USB ports indicated by suffixes 1 and 2 in the USB 
pin names and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.

 

The USB device interface can be routed to either USB port1 (using USB_CONNECT1, 
USB_UP_LED1, USB_D+1, USB_D

−1) or USB port2 (using USB_CONNECT2, 

USB_UP_LED2, USB_D+2, USB_D

−2) to allow for more versatile pin multiplexing (see 

To use both ports for USB transfer, port1 has to be configured as host and port2 has to be 
configured as device. See 

 for details. 

The USB device/host/OTG controller is disabled after RESET and must be enabled by 
writing a 1 to the PCUSB bit in the PCONP register, see 

.

This section describes the clocking and power management features of the USB Device 
Controller.

V

BUS

I

V

BUS

 status input. When this function is not enabled 

via its corresponding PINSEL register, it is driven 
HIGH internally.

USB_CONNECT1, 
USB_CONNECT2

O

SoftConnect control signal.

USB_UP_LED1, 
USB_UP_LED2

O

GoodLink LED control signal.

USB_D+1, USB_D+2

I/O

Positive differential data.

USB_D

−1, USB_D−2

I/O

Negative differential data.