Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The CAN controller in available on parts LPC2458 and LPC2460/68/70/78.

The CAN1/2 peripherals are configured using the following registers:

1. Power: In the PCONP register (

), set bits PCAN1/2.

Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0).

2. Peripheral clock: In the PCLK_SEL0 register (

), select PCLK_CAN1/2 and, 

for the acceptance filter, PCLK_ACF.

Remark: If CAN baudrates above 100 kbit/s (see 

) are needed, do not 

select the IRC as the clock source (see 

).

3. Wakeup: Use the INTWAKE register (

) to enable the CAN controllers to 

wake up the microcontroller from Power-down mode.

4. Pins: Select CAN1/2 pins and pin modes in registers PINSELn and PINMODEn (see 

5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers 

). Interrupts are enabled in the VIC using the VICIntEnable register 

).

6. CAN controller initialization: see CANMOD register (

).

Controller Area Network (CAN) is the definition of a high performance communication 
protocol for serial data communication. The CAN Controller is designed to provide a full 
implementation of the CAN-Protocol according to the CAN Specification Version 2.0B. 
Microcontrollers with this on-chip CAN controller are used to build powerful local networks 
by supporting distributed real-time control with a very high level of security. The 
applications are automotive, industrial environments, and high speed networks as well as 
low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced 
diagnostic and supervisory capabilities.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the 
device to be used as a gateway, switch, or router among a number of CAN buses in 
various applications.

The CAN module consists of two elements: the controller and the Acceptance Filter. All 
registers and the RAM are accessed as 32 bit words.