Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
495 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up
in response to bus activity, is not able to receive an initial message, until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is
active when software sets SM, the wake-up is immediate.
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up
in response to bus activity, is not able to receive an initial message, until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is
active when software sets SM, the wake-up is immediate.
9.3 Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”.
The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each
Receive and Transmit interrupt request from each controller is assigned its own channel in
the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The
“other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr
condition, are ORed into one VIC channel.
The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each
Receive and Transmit interrupt request from each controller is assigned its own channel in
the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The
“other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr
condition, are ORed into one VIC channel.
9.4 Transmit priority
If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the
right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,
they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both
cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have
the same smallest value, the lowest-numbered buffer sends first.
right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,
they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both
cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have
the same smallest value, the lowest-numbered buffer sends first.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it
sends each message.
sends each message.
10. Centralized CAN registers
For easy and fast access, all CAN Controller Status bits from each CAN Controller Status
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
All Status registers are “read-only” and allow byte, half word and word access.
10.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
Table 438. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit
Symbol
Description
Reset
Value
Value
0
TS1
When 1, the CAN controller 1 is sending a message (same as TS in the
CAN1GSR).
CAN1GSR).
0
1
TS2
When 1, the CAN controller 2 is sending a message (same as TS in the
CAN2GSR)
CAN2GSR)
0
7:2
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
8
TBS1
When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU
(same as TBS in CAN1GSR).
(same as TBS in CAN1GSR).
1
9
TBS2
When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU
(same as TBS in CAN2GSR).
(same as TBS in CAN2GSR).
1