Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

The adapter register block contains all system registers. This block also generates the 
signals that clear the static flags in the multimedia card. The clear signals are generated 
when 1 is written into the corresponding bit location of the MCIClear register.

The control unit contains the power management functions and the clock divider for the 
memory card clock.

There are three power phases:

Power-off

Power-up

Power-on

The power management logic controls an external power supply unit, and disables the 
card bus output signals during the power-off or power-up phases. The power-up phase is 
a transition phase between the power-off and power-on phases, and allows an external 
power supply to reach the card bus operating voltage. A device driver is used to ensure 
that the PrimeCell MCI remains in the power-up phase until the external power supply 
reaches the operating voltage.

The clock management logic generates and controls the MCICLK signal. The MCICLK 
output can use either a clock divide or clock bypass mode. The clock output is inactive:

after reset

during the power-off or power-up phases

if the power saving mode is enabled and the card bus is in the IDLE state (eight clock 
periods after both the command and data path subunits enter the IDLE phase)

The command path subunit sends commands to and receives responses from the cards.

When the command register is written to and the enable bit is set, command transfer 
starts. When the command has been sent, the Command Path State Machine (CPSM) 
sets the status flags and enters the IDLE state if a response is not required. If a response 
is required, it waits for the response (see 

). When the response is received, 

the received CRC code and the internally generated code are compared, and the 
appropriate status flags are set.