Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
628 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
6.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
6.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028,
0xE007 0028, 0xE007 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 551: Capture Control Register (T[0/1/2/3]CCR - addresses 0xE000 4028, 0xE000 8020,
0xE007 0028, 0xE007 4028) bit description
Bit
Symbol
Value Description
Reset
Value
Value
0
CAP0RE 1
Capture on CAPn.0 rising edge: a sequence of 0 then 1 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
CAPn.0 will cause CR0 to be loaded with the contents of TC.
0
0
This feature is disabled.
1
CAP0FE 1
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
CAPn.0 will cause CR0 to be loaded with the contents of TC.
0
0
This feature is disabled.
2
CAP0I
1
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event
will generate an interrupt.
will generate an interrupt.
0
0
This feature is disabled.
3
CAP1RE 1
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
CAPn.1 will cause CR1 to be loaded with the contents of TC.
0
0
This feature is disabled.
4
CAP1FE 1
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
CAPn.1 will cause CR1 to be loaded with the contents of TC.
0
0
This feature is disabled.
5
CAP1I
1
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event
will generate an interrupt.
will generate an interrupt.
0
0
This feature is disabled.
15:6
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA