Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
629 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C)
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0,1, 2, or 3, and “m” represent
a Match number, 0 through 3.
In the descriptions below, “n” represents the Timer number, 0,1, 2, or 3, and “m” represent
a Match number, 0 through 3.
Table 552: External Match Register (T[0/1/2/3]EMR - addresses 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C) bit description
Bit
Symbol Description
Reset
Value
Value
0
EM0
External Match 0. When a match occurs between the TC and MR0, this
bit can either toggle, go low, go high, or do nothing, depending on bits 5:4
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
bit can either toggle, go low, go high, or do nothing, depending on bits 5:4
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
0
1
EM1
External Match 1. When a match occurs between the TC and MR1, this
bit can either toggle, go low, go high, or do nothing, depending on bits 7:6
of this register. This bit can be driven onto a MATn.1 pin, in a
positive-logic manner (0 = low, 1 = high).
bit can either toggle, go low, go high, or do nothing, depending on bits 7:6
of this register. This bit can be driven onto a MATn.1 pin, in a
positive-logic manner (0 = low, 1 = high).
0
2
EM2
External Match 2. When a match occurs between the TC and MR2, this
bit can either toggle, go low, go high, or do nothing, depending on bits 9:8
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
bit can either toggle, go low, go high, or do nothing, depending on bits 9:8
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
0
3
EM3
External Match 3. When a match occurs between the TC and MR3, this
bit can either toggle, go low, go high, or do nothing, depending on bits
11:10 of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
bit can either toggle, go low, go high, or do nothing, depending on bits
11:10 of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
0
5:4
EMC0
External Match Control 0. Determines the functionality of External Match
0.
0.
shows the encoding of these bits.
00
7:6
EMC1
External Match Control 1. Determines the functionality of External Match
1.
1.
shows the encoding of these bits.
00
9:8
EMC2
External Match Control 2. Determines the functionality of External Match
2.
2.
shows the encoding of these bits.
00
11:10 EMC3
External Match Control 3. Determines the functionality of External Match
3.
3.
shows the encoding of these bits.
00
15:12 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
Table 553. External Match Control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
EMR[7:6], or EMR[5:4]
Function
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (MATn.m pin is
LOW if pinned out).
LOW if pinned out).
10
Set the corresponding External Match bit/output to 1 (MATn.m pin is
HIGH if pinned out).
HIGH if pinned out).
11
Toggle the corresponding External Match bit/output.