Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

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If the buffers are enabled, an AHB write operation writes into the Least Recently Used 
(LRU) buffer, if empty.

If the LRU buffer is not empty, the contents of the buffer are flushed to memory to 
make space for the AHB write data.

If a buffer contains write data it is marked as dirty, and its contents are written to 
memory before the buffer can be reallocated.

The write buffers are flushed whenever:

The memory controller state machine is not busy performing accesses to external 
memory.

The memory controller state machine is not busy performing accesses to external 
memory, and an AHB interface is writing to a different buffer.

Note: For dynamic memory, the smallest buffer flush is a quadword of data. For static 
memory, the smallest buffer flush is a byte of data.

Read buffers are used to:

Buffer read requests from memory. Future read requests that hit the buffer read the 
data from the buffer rather than memory, reducing transaction latency.

Convert all read transactions into quadword bursts on the external memory interface. 
This enhances transfer efficiency for dynamic memory.

Reduce external memory traffic. This improves memory bandwidth and reduces 
power consumption.

Read buffer operation:

If the buffers are enabled and the read data is contained in one of the buffers, the read 
data is provided directly from the buffer.

If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is 
dirty (contains write data), the write data is flushed to memory. When an empty buffer 
is available the read command is posted to the memory.

A buffer filled by performing a read from memory is marked as not-dirty (not containing 
write data) and its contents are not flushed back to the memory controller unless a 
subsequent AHB transfer performs a write that hits the buffer.

The memory controller state machine comprises a static memory controller and a dynamic 
memory controller.

In many systems, the contents of the memory system have to be maintained during 
low-power sleep modes. The EMC provides a mechanism to place the dynamic memories 
into self-refresh mode.