Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
72 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
Self-refresh mode can be entered by software by setting the SREFREQ bit in the
EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register.
EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register.
Any transactions to memory that are generated while the memory controller is in
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to
normal operation. See the memory data sheet for refresh requirements.
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to
normal operation. See the memory data sheet for refresh requirements.
Note: The static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.
self-refresh mode.
6.1 Low-power SDRAM Deep-sleep Mode
The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can
be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit
(CE), and the dynamic clock control bit (CS) in the EMCDynamicControl register. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit
(CE), and the dynamic clock control bit (CS) in the EMCDynamicControl register. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
6.2 Low-power SDRAM partial array refresh
The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
7.
Memory bank select
Eight independently-configurable memory chip selects are supported:
•
Pins CSn3 to CSn0 are used to select static memory devices.
•
Pins DYCSn3 to DYCSn0 are used to select dynamic memory devices.
Static memory chip select ranges are each 16 megabytes in size, while dynamic memory
chip selects cover a range of 256 megabytes each.
chip selects cover a range of 256 megabytes each.
shows the address ranges
of the chip selects.
Table 65.
Memory bank selection
Chip select pin
Address range
Memory type
Size of range
CS0
0x8000 0000 - 0x80FF FFFF
Static
16 MB
CS1
0x8100 0000 - 0x81FF FFFF
Static
16 MB
CS2
0x8200 0000 - 0x82FF FFFF
Static
16 MB
CS3
0x8300 0000 - 0x83FF FFFF
Static
16 MB
DYCS0
0xA000 0000 - 0xAFFF FFFF
Dynamic
256 MB
DYCS1
0xB000 0000 - 0xBFFF FFFF
Dynamic
256 MB
DYCS2
0xC000 0000 - 0xCFFF FFFF
Dynamic
256 MB
DYCS3
0xD000 0000 - 0xDFFF FFFF
Dynamic
256 MB