Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

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Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

The EMCControl register is a read/write register that controls operation of the memory 
controller. The control bits can be altered during normal operation. 

 shows the 

bit assignments for the EMCControl register.

 

0xFFE0 8268

EMCStatic WaitOen3

Selects the delay from chip select 3 or address change, 
whichever is later, to output enable.

-

0x0

R/W

0xFFE0 826C

EMCStatic WaitRd3

Selects the delay from chip select 3 to a read access.

-

0x1F

R/W

0xFFE0 8270

EMCStatic WaitPage3

Selects the delay for asynchronous page mode 
sequential accesses for chip select 3.

-

0x1F

R/W

0xFFE0 8274

EMCStatic WaitWr3

Selects the delay from chip select 3 to a write access.

-

0x1F

R/W

0xFFE0 8278

EMCStatic WaitTurn3

Selects the number of bus turnaround cycles for chip 
select 3.

-

0xF

R/W

0

EMC Enable (E)

Indicates if the EMC is enabled or disabled:

1

0

Disabled

1

Enabled (POR and warm reset value).

Disabling the EMC reduces power consumption. 
When the memory controller is disabled the memory 
is not refreshed. The memory controller is enabled by 
setting the enable bit, or by reset.

This bit must only be modified when the EMC is in idle 
state.

1

Address mirror (M)

Indicates normal or reset memory map:

1

0

Normal memory map.

1

Reset memory map. Static memory CS1 is mirrored 
onto CS0 and DYCS0 (POR reset value).

On POR, CS1 is mirrored to both CS0 and DYCS0 
memory areas. Clearing the M bit enables CS0 and 
DYCS0 memory to be accessed.