Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
91
7.7 Time/Date Clock (Real-Time Clock)
The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz
oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters.
The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits.
The time for this ripple to take place is a few nanoseconds per bit, and certainly should not
should not exceed 200 ns for all 8 bits, even when operating at low voltage.
oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters.
The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits.
The time for this ripple to take place is a few nanoseconds per bit, and certainly should not
should not exceed 200 ns for all 8 bits, even when operating at low voltage.
The 48 bits are enough to count up 272 years at the 32 kHz clock frequency. By conven-
tion, 12 AM on January 1, 1980, is taken as time zero. Z-World software ignores the high-
est order bit, giving the counter a capacity of 136 years from January 1, 1980. To read the
counter value, the value is first transferred to a 6-byte holding register. Then the individual
bytes may be read from the holding registers. To perform the transfer, any data bits are
written to RTC0R, the first holding register. The counter may then be read as six 8-bit
bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator are powered from
a separate power pin that can be provided with power while the remainder of the chip is
powered down. This design makes battery backup possible. Since the processor operates
on a different clock than the RTC, there is the possibility of performing a transfer to the
holding registers while a carry is taking place, resulting in incorrect information. In order
to prevent this, the processor should do the clock read twice and make sure that the value
is the same in both reads.
tion, 12 AM on January 1, 1980, is taken as time zero. Z-World software ignores the high-
est order bit, giving the counter a capacity of 136 years from January 1, 1980. To read the
counter value, the value is first transferred to a 6-byte holding register. Then the individual
bytes may be read from the holding registers. To perform the transfer, any data bits are
written to RTC0R, the first holding register. The counter may then be read as six 8-bit
bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator are powered from
a separate power pin that can be provided with power while the remainder of the chip is
powered down. This design makes battery backup possible. Since the processor operates
on a different clock than the RTC, there is the possibility of performing a transfer to the
holding registers while a carry is taking place, resulting in incorrect information. In order
to prevent this, the processor should do the clock read twice and make sure that the value
is the same in both reads.
If the processor is itself operating at 32 kHz, the read-clock procedure must be modified
since a number of clock counts would take place in the time needed by the slow-clocked
processor to read the clock. An appropriate modification would be to ignore the lower
bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every
1/128th of a second. If the read cannot be performed in this time, further low-order bits
can be ignored.
since a number of clock counts would take place in the time needed by the slow-clocked
processor to read the clock. An appropriate modification would be to ignore the lower
bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every
1/128th of a second. If the read cannot be performed in this time, further low-order bits
can be ignored.
The RTC registers cannot be set by a write operation, but they can be cleared and counted
individually, or by subset. In this manner, any register or the entire 48-bit counter can be
set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the
input pin is grounded, no counting will take place and the six registers can be used as a
small battery-backed memory. Normally this would not be very productive since the cir-
cuitry needed to provide the power switchover could also be used to battery-back a regular
low-power static RAM.
individually, or by subset. In this manner, any register or the entire 48-bit counter can be
set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the
input pin is grounded, no counting will take place and the six registers can be used as a
small battery-backed memory. Normally this would not be very productive since the cir-
cuitry needed to provide the power switchover could also be used to battery-back a regular
low-power static RAM.