Jameco Electronics 3000 ユーザーズマニュアル
2
Rabbit 3000 Microprocessor
1.1 Features and Specifications Rabbit 3000
•
128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All
specifications are given for both industrial and commercial temperature and voltage
ranges. Rabbit microprocessors are low-cost.
specifications are given for both industrial and commercial temperature and voltage
ranges. Rabbit microprocessors are low-cost.
•
Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to
+85°C. Modified commercial specifications are for a voltage variation of 5% and a
temperature range from -40°C to 70°C.
+85°C. Modified commercial specifications are for a voltage variation of 5% and a
temperature range from -40°C to 70°C.
•
1-megabyte code-data space allows C programs with 50,000+ lines of code. The
extended Z80-style instruction set is C-friendly, with short and fast opcodes for the
most important C operations.
extended Z80-style instruction set is C-friendly, with short and fast opcodes for the
most important C operations.
•
Four levels of interrupt priority make a fast interrupt response practical for critical
applications. The maximum time to the first instruction of an interrupt routine is about
0.5 µs at a clock speed of 50 MHz.
applications. The maximum time to the first instruction of an interrupt routine is about
0.5 µs at a clock speed of 50 MHz.
•
Access to I/O devices is accomplished by using memory access instructions with an I/O
prefix. Access to I/O devices is thus faster and easier compared to processors with a
distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be
enabled to use separate pins for address and data, allowing the I/O bus to have a greater
physical extent with less EMI and less conflict with the requirements of the fast mem-
ory bus.(Further described below.)
prefix. Access to I/O devices is thus faster and easier compared to processors with a
distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be
enabled to use separate pins for address and data, allowing the I/O bus to have a greater
physical extent with less EMI and less conflict with the requirements of the fast mem-
ory bus.(Further described below.)
•
Hardware design is simple. Up to six static memory chips (such as RAM and flash
memory) connect directly to the microprocessor with no glue logic. A memory-access
time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns
memory-access time, a clock speed of up to 50 MHz is possible with no wait states.
Most I/O devices may be connected without glue logic.
memory) connect directly to the microprocessor with no glue logic. A memory-access
time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns
memory-access time, a clock speed of up to 50 MHz is possible with no wait states.
Most I/O devices may be connected without glue logic.
The memory read cycle is two clocks long. The write cycle is 3 clocks long. A clean
memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O
devices can usually be interfaced in a glueless fashion using the common /IORD and
/IOWR strobes in addition to the user-configurable IO strobes on Parallel Port E. The
Parallel Port E pins can be configured as I/O read, write, read/write, or chip select when
they are used as I/O strobes.
memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O
devices can usually be interfaced in a glueless fashion using the common /IORD and
/IOWR strobes in addition to the user-configurable IO strobes on Parallel Port E. The
Parallel Port E pins can be configured as I/O read, write, read/write, or chip select when
they are used as I/O strobes.
•
EMI reduction features reduce EMI levels by as much as 25 dB compared to other sim-
ilar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-fre-
quency noise generated in the processor core from propagating to the signal output
pins. A built-in clock spectrum spreader reduces electromagnetic interference and facil-
itates passing EMI tests to prove compliance with government regulatory requirements.
As a consequence, the designer of a Rabbit-3000-based system can be assured of pass-
ing FCC or CE EMI tests as long as minimal design precautions are followed.
ilar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-fre-
quency noise generated in the processor core from propagating to the signal output
pins. A built-in clock spectrum spreader reduces electromagnetic interference and facil-
itates passing EMI tests to prove compliance with government regulatory requirements.
As a consequence, the designer of a Rabbit-3000-based system can be assured of pass-
ing FCC or CE EMI tests as long as minimal design precautions are followed.
•
The Rabbit may be cold-booted via a serial port or the parallel access slave port. This
means that flash program memory may be soldered in unprogrammed, and can be
reprogrammed at any time without any assumption of an existing program or BIOS.
means that flash program memory may be soldered in unprogrammed, and can be
reprogrammed at any time without any assumption of an existing program or BIOS.