Jameco Electronics 3000 ユーザーズマニュアル
140
Rabbit 3000 Microprocessor
9.6 Parallel Port F
Parallel Port F is a byte-wide port with each bit programmable for data direction and drive.
These are simple inputs and outputs controlled and reported in the Port F Data Register.
As outputs, the bits of the port are buffered, with the data written to the Port F Data Regis-
ter transferred to the output pins on a selected timing edge. The outputs of Timer A1,
Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a
separate select field to control this timing.
These are simple inputs and outputs controlled and reported in the Port F Data Register.
As outputs, the bits of the port are buffered, with the data written to the Port F Data Regis-
ter transferred to the output pins on a selected timing edge. The outputs of Timer A1,
Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a
separate select field to control this timing.
These inputs and outputs are also used for access to other peripherals on the chip. As out-
puts, the Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As
inputs, Parallel Port F inputs can carry the inputs to the quadrature decoders. When Serial
Port C or Serial Port D is used in the clocked serial mode, two pins of Parallel Port F are
used to carry the serial clock signals. When the internal clock is selected in these serial
ports, the corresponding bit of Parallel Port F is set as an output.
puts, the Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As
inputs, Parallel Port F inputs can carry the inputs to the quadrature decoders. When Serial
Port C or Serial Port D is used in the clocked serial mode, two pins of Parallel Port F are
used to carry the serial clock signals. When the internal clock is selected in these serial
ports, the corresponding bit of Parallel Port F is set as an output.
The Parallel Port F registers and their functions are described in Table 9-14 and in Table 9-15.
Table 9-13. Parallel Port F Registers
Register Name
Mnemonic
I/O address
R/W
Reset
Port F Data Register
PFDR
0x38
R/W
xxxxxxxx
Port F Control Register
PFCR
0x3C
W
xx00xx00
Port F Function Register
PFFR
0x3D
W
xxxxxxxx
Port F Drive Control Register
PFDCR
0x3E
W
xxxxxxxx
Port F Data Direction Register
PFDDR
0x3F
W
00000000
Table 9-14. Parallel Port F Register Functions
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFDR (R/W)
adr = 0x038
adr = 0x038
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PFFR (W)
adr = 0x03D
adr = 0x03D
pwm[3]
pwm[2]
pwm[1]
pwm[0]
x
x
sclk_c
sclk_d
PFDCR (W)
adr = 0x03E
adr = 0x03E
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
out =
open
drain
open
drain
PFDDR (W)
adr = 0x03F
adr = 0x03F
dir =
out
out
dir =
out
out
dir =
out
out
dir =
out
out
dir =
out
out
dir =
out
out
dir =
out
out
dir =
out
out