Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
243
18.3 Shadow Registers
Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates
on the chip, making possible greater capability at lower cost. Write-only registers are eas-
ier to use if a memory location, called a shadow register, is associated with each write-
only register. To make shadow register names easy to remember, the word shadow is
appended to the register name. For example the register GOCR (Global Output Control
register) has the shadow
on the chip, making possible greater capability at lower cost. Write-only registers are eas-
ier to use if a memory location, called a shadow register, is associated with each write-
only register. To make shadow register names easy to remember, the word shadow is
appended to the register name. For example the register GOCR (Global Output Control
register) has the shadow
GOCRShadow
. Some shadow registers are defined in the BIOS
source code as shown below.
char GCSRShadow; // Global Control Status Register
char GOCRShadow; // Global Output Control Registe
r
char GCDRShadow; // Global Clock Doubler Register
If the port is a write-only port, the shadow register can be used to find out the port’s con-
tents. For example GCSR has a number of write-only bits. These can be read by consult-
ing the shadow, provided that the shadow register is always updated when writing to the
register.
tents. For example GCSR has a number of write-only bits. These can be read by consult-
ing the shadow, provided that the shadow register is always updated when writing to the
register.
k=GCSRShadow;
18.3.1 Updating Shadow Registers
If the address of a shadow register is passed as an argument to one of the functions that
write to the internal or external I/O registers, then the shadow register will be updated as
well as the specified I/O register.
write to the internal or external I/O registers, then the shadow register will be updated as
well as the specified I/O register.
A
NULL
pointer may replace the pointer to a shadow register as an argument to
WrPortI()
and
WrPortE()
; the shadow register associated with the port will not be updated. A pointer
to the shadow register is mandatory for
BitWrPortI()
and
BitWrPortE()
.
18.3.2 Interrupt While Updating Registers
When manipulating I/O registers and shadow registers, the programmer must keep in
mind that an interrupt can take place in the middle of the sequence of operations, and then
the interrupt routine may manipulate the same registers. If this possibility exists, then a
solution must be crafted for the particular situation. Usually it is not necessary to disable
the interrupts while manipulating registers and their associated shadow registers.
mind that an interrupt can take place in the middle of the sequence of operations, and then
the interrupt routine may manipulate the same registers. If this possibility exists, then a
solution must be crafted for the particular situation. Usually it is not necessary to disable
the interrupts while manipulating registers and their associated shadow registers.
18.3.2.1 Atomic Instruction
As an example, consider the Parallel Port D data direction register (PDDDR). This register
is write only, and it contains 8 bits corresponding to the 8 I/O pins of Parallel Port D. If a
bit in this register is a “1,” the corresponding port pin is an output, otherwise it is an input.
It is easy to imagine a situation where different parts of the application, such as an inter-
rupt routine and a background routine, need to be in charge of different bits in the PDDDR
register. The following code sets a bit in the shadow and then sets the I/O register. If an
interrupt takes place between the
is write only, and it contains 8 bits corresponding to the 8 I/O pins of Parallel Port D. If a
bit in this register is a “1,” the corresponding port pin is an output, otherwise it is an input.
It is easy to imagine a situation where different parts of the application, such as an inter-
rupt routine and a background routine, need to be in charge of different bits in the PDDDR
register. The following code sets a bit in the shadow and then sets the I/O register. If an
interrupt takes place between the
set
and the
LDD
, and changes the shadow register and
PDDDR, the correct value will still be set in PDDDR.