Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
273
A
PPENDIX
B. R
ABBIT
3000 R
EVISIONS
Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revi-
sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit
3000 revisions are pin-compatible, and transparently replace previous versions of the chip.
sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit
3000 revisions are pin-compatible, and transparently replace previous versions of the chip.
The Rabbit 3000 has been supplied in the following versions.
1. Original Rabbit 3000—Available in two packages and identified by IL1T for the
LQFP package and IZ1T for the TFBGA package. The LQFP package began shipping
in March 2002, and the TFBGA package began shipping in January 2003. There were
several bugs:
in March 2002, and the TFBGA package began shipping in January 2003. There were
several bugs:
(a) Port A decode bug—This bug is documented in TN228, Rabbit 3000 Parallel
Port F Bug. The problem involves an incomplete address decode of the data
output register for Parallel Port A. If Parallel Port A is used as an output or is
used as the bidirectional bus for the slave port, then writing to any of the Paral-
lel Port F registers will cause a spurious write to the Parallel Port A register.
output register for Parallel Port A. If Parallel Port A is used as an output or is
used as the bidirectional bus for the slave port, then writing to any of the Paral-
lel Port F registers will cause a spurious write to the Parallel Port A register.
(b) LDIR/LDDR with wait states—This bug is documented in Section 19.16. The
nature of the problem is such that first iteration of LDIR/LDDR uses the cor-
rect number of wait states for both the read and the write. However, all subse-
quent iterations use the number of waits programmed for the memory located
at the write address for both the read and the write cycles. This becomes a
problem when moving a block of data from a slow memory device requiring
wait states to a fast memory device requiring no wait states.
rect number of wait states for both the read and the write. However, all subse-
quent iterations use the number of waits programmed for the memory located
at the write address for both the read and the write cycles. This becomes a
problem when moving a block of data from a slow memory device requiring
wait states to a fast memory device requiring no wait states.
(c) Interrupt after I/O with Short /CSx enabled—This bug is documented in
Section 7.5. When the short chip select option is enabled, the interrupt
sequence will attempt to write the return address to the stack if an interrupt
takes place immediately after an internal or an external I/O instruction. The
chip select will be suppressed during the write cycle, and the correct return
address will not be stored on the stack. This happens only when an interrupt
takes place immediately after an I/O instruction when the short chip select
option is enabled.
sequence will attempt to write the return address to the stack if an interrupt
takes place immediately after an internal or an external I/O instruction. The
chip select will be suppressed during the write cycle, and the correct return
address will not be stored on the stack. This happens only when an interrupt
takes place immediately after an I/O instruction when the short chip select
option is enabled.
(d) IrDA bug—This bug is documented in TN236, Rabbit 3000 IrDA Bug. When
configured to operate in the IrDA mode, the serial port may at times generate
an extra pulse before the start bit is transmitted. This pulse may appear either
before a multi-character transmission or before a single-character transmission.
If the beginning of the start bit coincides with when the IrDA pulse generator
output is high, there will be a spurious 1/16th-bit cell pulse on the transmit
output.
an extra pulse before the start bit is transmitted. This pulse may appear either
before a multi-character transmission or before a single-character transmission.
If the beginning of the start bit coincides with when the IrDA pulse generator
output is high, there will be a spurious 1/16th-bit cell pulse on the transmit
output.