Jameco Electronics 3000 ユーザーズマニュアル
Rabbit 3000 Microprocessor
3.5 Interrupt Structure .............................................................................................................................. 44
3.5.1 Interrupt Priority ........................................................................................................................ 44
3.5.2 Multiple External Interrupting Devices ..................................................................................... 46
3.5.3 Privileged Instructions, Critical Sections and Semaphores ....................................................... 46
3.5.4 Critical Sections ......................................................................................................................... 47
3.5.5 Semaphores Using Bit B,(HL) .................................................................................................. 47
3.5.6 Computed Long Calls and Jumps .............................................................................................. 48
3.5.2 Multiple External Interrupting Devices ..................................................................................... 46
3.5.3 Privileged Instructions, Critical Sections and Semaphores ....................................................... 46
3.5.4 Critical Sections ......................................................................................................................... 47
3.5.5 Semaphores Using Bit B,(HL) .................................................................................................. 47
3.5.6 Computed Long Calls and Jumps .............................................................................................. 48
4.1 Precisely Timed Output Pulses .......................................................................................................... 49
4.2 Open-Drain Outputs Used for Key Scan............................................................................................ 51
4.3 Cold Boot ........................................................................................................................................... 52
4.4 The Slave Port .................................................................................................................................... 53
4.3 Cold Boot ........................................................................................................................................... 52
4.4 The Slave Port .................................................................................................................................... 53
5.1 LQFP Package.................................................................................................................................... 56
5.1.1 Pinout ......................................................................................................................................... 56
5.1.2 Mechanical Dimensions and Land Pattern ................................................................................ 57
5.1.2 Mechanical Dimensions and Land Pattern ................................................................................ 57
5.2 Ball Grid Array Package ................................................................................................................... 59
5.2.1 Pinout ......................................................................................................................................... 59
5.2.2 Mechanical Dimensions and Land Pattern ................................................................................ 60
5.2.2 Mechanical Dimensions and Land Pattern ................................................................................ 60
5.3 Rabbit Pin Descriptions...................................................................................................................... 62
5.4 Bus Timing ......................................................................................................................................... 64
5.5 Description of Pins with Alternate Functions .................................................................................... 65
5.6 DC Characteristics.............................................................................................................................. 68
5.7 I/O Buffer Sourcing and Sinking Limit.............................................................................................. 69
5.4 Bus Timing ......................................................................................................................................... 64
5.5 Description of Pins with Alternate Functions .................................................................................... 65
5.6 DC Characteristics.............................................................................................................................. 68
5.7 I/O Buffer Sourcing and Sinking Limit.............................................................................................. 69
6.1 Default Values for all the Peripheral Control Registers..................................................................... 73
7.1 Processor Identification...................................................................................................................... 79
7.2 Rabbit Oscillators and Clocks ............................................................................................................ 80
7.3 Clock Doubler .................................................................................................................................... 83
7.4 Clock Spectrum Spreader................................................................................................................... 86
7.5 Chip Select Options for Low Power .................................................................................................. 87
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN .......................................................................... 90
7.7 Time/Date Clock (Real-Time Clock) ................................................................................................. 91
7.8 Watchdog Timer................................................................................................................................. 93
7.9 System Reset ...................................................................................................................................... 95
7.10 Rabbit Interrupt Structure................................................................................................................. 97
7.2 Rabbit Oscillators and Clocks ............................................................................................................ 80
7.3 Clock Doubler .................................................................................................................................... 83
7.4 Clock Spectrum Spreader................................................................................................................... 86
7.5 Chip Select Options for Low Power .................................................................................................. 87
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN .......................................................................... 90
7.7 Time/Date Clock (Real-Time Clock) ................................................................................................. 91
7.8 Watchdog Timer................................................................................................................................. 93
7.9 System Reset ...................................................................................................................................... 95
7.10 Rabbit Interrupt Structure................................................................................................................. 97
7.10.1 External Interrupts ................................................................................................................... 99
7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 .......................................................... 100
7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 .......................................................... 100
7.11 Bootstrap Operation ....................................................................................................................... 101
7.12 Pulse Width Modulator .................................................................................................................. 103
7.13 Input Capture.................................................................................................................................. 105
7.14 Quadrature Decoder ....................................................................................................................... 110
7.12 Pulse Width Modulator .................................................................................................................. 103
7.13 Input Capture.................................................................................................................................. 105
7.14 Quadrature Decoder ....................................................................................................................... 110
8.1 Interface for Static Memory Chips................................................................................................... 115
8.2 Memory Mapping Overview ............................................................................................................ 117
8.3 Memory-Mapping Unit .................................................................................................................... 117
8.4 Memory Interface Unit..................................................................................................................... 119
8.2 Memory Mapping Overview ............................................................................................................ 117
8.3 Memory-Mapping Unit .................................................................................................................... 117
8.4 Memory Interface Unit..................................................................................................................... 119