Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
43
A>B (!S & !V & !Z) v (S & V)
A<B (S & !V) v (!S & V & !Z)
A==B
A>=B
A<=B
Another method of doing signed compare is to first map the signed integers onto unsigned
integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been per-
formed by inverting bit 15 on both numbers, the comparisions can be done as if the num-
bers were unsigned integers. This avoids having to construct a jump tree to test the
overflow and sign flags. An example is shown below.
integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been per-
formed by inverting bit 15 on both numbers, the comparisions can be done as if the num-
bers were unsigned integers. This avoids having to construct a jump tree to test the
overflow and sign flags. An example is shown below.
; test HL>5 for signed integers
LD DE,65535-(5+0x08000) ; 5 mapped to unsigned integers
LD BC,0x08000
ADD HL,BC ; invert high bit
ADD HL,DE ; 16 clocks to here
; carry now set if HL>5 - opportunity to jump on carry
SUBC HL,HL ; HL-HL-C ; if C on result is -1, else zero
BOOL HL ; 22 clocks total - true if HL>5 else false
Figure 3-8. Mapping Signed Integers to Unsigned Integers by Inverting Bit 15
3.4.5 Atomic Moves from Memory to I/O Space
To avoid disabling interrupts while copying a shadow register to its target register, it is
desirable to have an atomic move from memory to I/O space. This can be done using LDD
or LDI instructions.
desirable to have an atomic move from memory to I/O space. This can be done using LDD
or LDI instructions.
LD HL,sh_PDDDR ; point to shadow register
LD DE,PDDDR ; set DE to point to I/O reg
SET 5,(HL) ; set bit 5 of shadow register
; use ldd instruction for atomic transfer
IOI ldd ; (io DE)<-(HL) HL--, DE--
When the LDD instruction is prefixed with an I/O prefix, the destination becomes the I/O
address specified by DE. The decrementing of HL and DE is a side effect. If the repeating
instructions LDIR and LDDR are used, interrupts can take place between successive itera-
tions. Word stores to I/O space can be used to set two I/O registers at adjacent addresses
with a single noninterruptable instruction.
address specified by DE. The decrementing of HL and DE is a side effect. If the repeating
instructions LDIR and LDDR are used, interrupts can take place between successive itera-
tions. Word stores to I/O space can be used to set two I/O registers at adjacent addresses
with a single noninterruptable instruction.
0111...
000...
111...
111...
100...
1111...
100...
011...
011...
000...