Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
3-3
General Operation
Figure 3-2. Infinite Impulse Response (IIR) Filter
Here, the output y(i) is determined by past output values and past input values. This is the
general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR)
filter can be obtained by setting coefficients a(k) to zero. In either case, the operations
involved in computing such a filter are multiplies and product summing. To show this point,
reduce the above equation to a simple, four-tap FIR filter, shown in Figure 3-3, in which
the accumulated sum is a sum of past data values and coefficients.
general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR)
filter can be obtained by setting coefficients a(k) to zero. In either case, the operations
involved in computing such a filter are multiplies and product summing. To show this point,
reduce the above equation to a simple, four-tap FIR filter, shown in Figure 3-3, in which
the accumulated sum is a sum of past data values and coefficients.
Figure 3-3. Four-Tap FIR Filter
3.3
General Operation
The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU)
and provides additional functionality for multiply-accumulate operations. By executing
MULS and MULU in the MAC, execution times are minimized and deterministic
compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if
no MAC hardware is present.
and provides additional functionality for multiply-accumulate operations. By executing
MULS and MULU in the MAC, execution times are minimized and deterministic
compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if
no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two
numbers, followed by the addition or subtraction of the product to or from the value in an
accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or
subtraction. Hardware support for saturation arithmetic can be enabled to minimize
software overhead when dealing with potential overflow conditions. Multiply-accumulate
operations support 16- or 32-bit input operands of the following formats:
numbers, followed by the addition or subtraction of the product to or from the value in an
accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or
subtraction. Hardware support for saturation arithmetic can be enabled to minimize
software overhead when dealing with potential overflow conditions. Multiply-accumulate
operations support 16- or 32-bit input operands of the following formats:
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
• Unsigned integers
• Signed, fixed-point, fractional numbers
The EMAC is optimized for single-cycle, pipelined 32x32 multiplications. For word- and
longword-sized integer input operands, the low-order 40 bits of the product are formed and
used with the destination accumulator. For fractional operands, the entire 64-bit product is
calculated and either truncated or rounded to the most-significant 40-bit result using the
round-to-nearest (even) method before it is combined with the destination accumulator.
longword-sized integer input operands, the low-order 40 bits of the product are formed and
used with the destination accumulator. For fractional operands, the entire 64-bit product is
calculated and either truncated or rounded to the most-significant 40-bit result using the
round-to-nearest (even) method before it is combined with the destination accumulator.
y i
( )
a
k
1
=
N 1
–
∑
=
k
( )y i k
–
(
)
b
k
0
=
N 1
–
∑
k
( )x i k
–
(
)
+
y i
( )
b k
( )x i k
–
(
)
k
0
=
3
∑
b 0
( )x i
( ) b 1
( )x i 1
–
(
) b 2
( )x i 2
–
(
) b 3
( )x i 3
–
(
)
+
+
+
=
=