ユーザーズマニュアル目次About This Book43Audience43Organization43Suggested Reading46General Information46ColdFire Documentation46Conventions47Acronyms and Abbreviations48Terminology Conventions49Revision History52Chapter 1 Overview571.1 MCF5282 Key Features57Figure 1-1. MCF5282 Block Diagram631.1.1 Version 2 ColdFire Core641.1.1.1 Cache64Table 1-1. Cache Configuration641.1.1.2 SRAM651.1.1.3 Flash651.1.1.4 Debug Module651.1.2 System Control Module661.1.3 External Interface Module (EIM)661.1.4 Chip Select671.1.5 Power Management671.1.6 General Input/Output Ports671.1.7 Interrupt Controllers (INTC0/INTC1)671.1.8 SDRAM Controller671.1.9 Test Access Port681.1.10 UART Modules681.1.11 DMA Timers (DTIM0-DTIM3)691.1.12 General-Purpose Timers (GPTA/GPTB)691.1.13 Periodic Interrupt Timers (PIT0-PIT3)691.1.14 Software Watchdog Timer701.1.15 Phase Locked Loop (PLL)701.1.16 DMA Controller701.1.17 Reset701.2 MCF5282-Specific Features711.2.1 Fast Ethernet Controller (FEC)711.2.2 FlexCAN711.2.3 I2C Bus711.2.4 Queued Serial Peripheral Interface (QSPI)711.2.5 Queued Analog-to-Digital Converter (QADC)71Chapter 2 ColdFire Core732.1 Processor Pipelines73Figure 2-1. ColdFire Processor Core Pipelines732.2 Processor Register Description742.2.1 User Programming Model742.2.1.1 Data Registers (D0-D7)752.2.1.2 Address Registers (A0-A6)752.2.1.3 Stack Pointer (A7)752.2.1.4 Program Counter (PC)75Figure 2-2. User Programming Model762.2.1.5 Condition Code Register (CCR)76Figure 2-3. Condition Code Register (CCR)76Table 2-1. CCR Field Descriptions762.2.2 EMAC Programming Model77Figure 2-4. EMAC Register Set772.2.3 Supervisor Programming Model77Figure 2-5. Supervisor Programming Model782.2.3.1 Status Register (SR)78Figure 2-6. Status Register78Table 2-2. SR Field Descriptions (continued)782.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7)792.2.3.3 Vector Base Register (VBR)802.2.3.4 Cache Control Register (CACR)802.2.3.5 Access Control Registers (ACR0, ACR1)802.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)802.3 Programming Model80Table 2-3. ColdFire CPU Registers (continued)802.4 Additions to the Instruction Set Architecture81Table 2-4. ISA Revision A+ New Instructions822.5 Exception Processing Overview82Table 2-5. Exception Vector Assignments (continued)832.6 Exception Stack Frame Definition84Figure 2-7. Exception Stack Frame Form84Table 2-6. Format Field Encodings84Table 2-7. Fault Status Encodings852.7 Processor Exceptions852.7.1 Access Error Exception852.7.2 Address Error Exception862.7.3 Illegal Instruction Exception862.7.4 Divide-By-Zero862.7.5 Privilege Violation862.7.6 Trace Exception862.7.7 Unimplemented Line-A Opcode872.7.8 Unimplemented Line-F Opcode872.7.9 Debug Interrupt872.7.10 RTE and Format Error Exception882.7.11 TRAP Instruction Exception882.7.12 Interrupt Exception882.7.13 Fault-on-Fault Halt882.7.14 Reset Exception88Figure 2-8. D0 Hardware Configuration Info89Table 2-8. D0 Hardware Configuration Info Field Description90Figure 2-9. D1 Hardware Configuration Info91Table 2-9. D1 Local Memory Hardware Configuration Information Field Description (continued)912.8 Instruction Execution Timing932.8.1 Timing Assumptions93Table 2-10. Misaligned Operand References942.8.2 MOVE Instruction Execution Times94Table 2-11. Move Byte and Word Execution Times95Table 2-12. Move Long Execution Times952.9 Standard One Operand Instruction Execution Times96Table 2-13. One Operand Instruction Execution Times962.10 Standard Two Operand Instruction Execution Times96Table 2-14. Two Operand Instruction Execution Times (continued)962.11 Miscellaneous Instruction Execution Times98Table 2-15. Miscellaneous Instruction Execution Times982.12 EMAC Instruction Execution Times99Table 2-16. EMAC Instruction Execution Times992.13 Branch Instruction Execution Times100Table 2-17. General Branch Instruction Execution Times100Table 2-18. BRA, Bcc Instruction Execution Times1002.14 ColdFire Instruction Set Architecture Enhancements100Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)1053.1 Multiply-Accumulate Unit105Figure 3-1. Multiply-Accumulate Functionality Diagram1063.2 Introduction to the MAC106Figure 3-2. Infinite Impulse Response (IIR) Filter107Figure 3-3. Four-Tap FIR Filter1073.3 General Operation107Figure 3-4. Fractional Alignment108Figure 3-5. Signed and Unsigned Integer Alignment1083.4 Memory Map/Register Set110Figure 3-6. EMAC Register Set1103.4.1 MAC Status Register (MACSR)110Figure 3-7. MAC Status Register (MACSR)110Table 3-1. MACSR Field Descriptions (continued)111Table 3-2. Summary of S/U, F/I, and R/T Control Bits1123.4.1.1 Fractional Operation Mode1123.4.2 Mask Register (MASK)1143.5 EMAC Instruction Set Summary116Table 3-3. EMAC Instruction Summary1163.5.1 EMAC Instruction Execution Times116Figure 3-8. EMAC-Specific OEP Sequence Stall1173.5.2 Data Representation117Figure 3-9. Two’s Complement, Signed Fractional Equation1183.5.3 MAC Opcodes118Chapter 4 Cache1254.1 Cache Features1254.2 Cache Physical Organization125Figure 4-1. Cache Block Diagram1274.3 Cache Operation1274.3.1 Interaction with Other Modules1274.3.2 Memory Reference Attributes1284.3.3 Cache Coherency and Invalidation1284.3.4 Reset1294.3.5 Cache Miss Fetch Algorithm/Line Fills129Table 4-1. Initial Fetch Offset vs. CLNF Bits129Table 4-2. Instruction Cache Operation as Defined by CACR[31, 10]1304.4 Cache Programming Model1314.4.1 Cache Registers Memory Map131Table 4-3. Memory Map of Cache Registers1314.4.2 Cache Registers1314.4.2.1 Cache Control Register (CACR)131Figure 4-2. Cache Control Register (CACR)132Table 4-4. CACR Field Descriptions (continued)132Table 4-5. Cache Configuration as Defined by CACR[31, 23, 22]134Table 4-6. Cache Invalidate All as Defined by CACR[23, 22, 21, 20]134Table 4-7. External Fetch Size Based on Miss Address and CLNF1354.4.2.2 Access Control Registers (ACR0, ACR1)135Figure 4-3. Access Control Registers (ACR0, ACR1)135Table 4-8. ACR Field Descriptions (continued)135Chapter 5 Static RAM (SRAM)1375.1 SRAM Features1375.2 SRAM Operation1375.3 SRAM Programming Model1375.3.1 SRAM Base Address Register (RAMBAR)138Figure 5-1. SRAM Base Address Register (RAMBAR)138Table 5-1. SRAM Base Address Register (continued)1385.3.2 SRAM Initialization1395.3.3 SRAM Initialization Code1405.3.4 Power Management140Table 5-2. Typical RAMBAR Setting Examples140Chapter 6 ColdFire Flash Module (CFM)1436.1 Features1436.2 Block Diagram144Figure 6-1. CFM Block Diagram1456.3 Memory Map146Figure 6-2. CFM Array Memory Map1466.3.1 CFM Configuration Field147Table 6-1. CFM Configuration Field1476.3.2 Flash Base Address Register (FLASHBAR)147Figure 6-3. Flash Base Address Register (FLASHBAR)149Table 6-2. FLASHBAR Field Descriptions1496.3.3 CFM Registers150Table 6-3. CFM Register Address Map1506.3.4 Register Descriptions1506.3.4.1 CFM Configuration Register (CFMCR)150Figure 6-4. CFM Module Configuration Register (CFMCR)150Table 6-4. CFMCR Field Descriptions1516.3.4.2 CFM Clock Divider Register (CFMCLKD)151Figure 6-5. CFM Clock Divider Register (CFMCLKD)151Table 6-5. CFMCLKD Field Descriptions1526.3.4.3 CFM Security Register (CFMSEC)152Figure 6-6. CFM Security Register (CFMSEC)152Table 6-6. CFMSEC Field Descriptions1536.3.4.4 CFM Protection Register (CFMPROT)154Figure 6-7. CFM Protection Register (CFMPROT)154Table 6-7. CFMPROT Field Descriptions154Figure 6-8. CFMPROT Protection Diagram1556.3.4.5 CFM Supervisor Access Register (CFMSACC)155Figure 6-9. CFM Supervisor Access Register (CFMSACC)155Table 6-8. CFMSACC Field Descriptions1566.3.4.6 CFM Data Access Register (CFMDACC)156Figure 6-10. CFM Data Access Register (CFMDACC)156Table 6-9. CFMDACC Field Descriptions1566.3.4.7 CFM User Status Register (CFMUSTAT)157Figure 6-11. CFM User Status Register (CFMUSTAT)157Table 6-10. CFMUSTAT Field Descriptions1576.3.4.8 CFM Command Register (CFMCMD)158Figure 6-12. CFM Command Register (CFMCMD)158Table 6-11. CFMCMD Field Descriptions158Table 6-12. CFMCMD User Mode Commands1586.4 CFM Operation1596.4.1 Read Operations1596.4.2 Write Operations1596.4.3 Program and Erase Operations1596.4.3.1 Setting the CFMCLKD Register1606.4.3.2 Program, Erase, and Verify Sequences1616.4.3.3 Flash Valid Commands162Table 6-13. Flash User Commands162Figure 6-13. Example Program Algorithm1636.4.3.4 Flash User Mode Illegal Operations1646.4.4 Stop Mode1646.4.5 Master Mode1656.5 Flash Security Operation1656.5.1 Back Door Access1666.5.2 Erase Verify Check1666.6 Reset1666.7 Interrupts167Table 6-14. CFM Interrupt Sources167Chapter 7 Power Management1697.1 Features1697.2 Memory Map and Registers1697.2.1 Programming Model1697.2.2 Memory Map170Table 7-1. Chip Configuration Module Memory Map1707.2.3 Register Descriptions1707.2.3.1 Low-Power Interrupt Control Register (LPICR)170Figure 7-1. Low-Power Interrupt Control Register (LPICR)171Table 7-2. LPICR Field Description171Table 7-3. XLPM_IPL Settings1727.2.3.2 Low-Power Control Register (LPCR)172Figure 7-2. Low-Power Control Register (LPCR)172Table 7-4. LPCR Field Descriptions172Table 7-5. Low-Power Modes173Table 7-6. PLL/CLKOUT Stop Mode Operation1737.3 Functional Description1737.3.1 Low-Power Modes1737.3.1.1 Run Mode1747.3.1.2 Wait Mode1747.3.1.3 Doze Mode1747.3.1.4 Stop Mode1747.3.1.5 Peripheral Shut Down1757.3.2 Peripheral Behavior in Low-Power Modes1757.3.2.1 ColdFire Core1757.3.2.2 Static Random-Access Memory (SRAM)1757.3.2.3 Flash1757.3.2.4 System Control Module (SCM)1757.3.2.5 SDRAM Controller (SDRAMC)1767.3.2.6 Chip Select Module1767.3.2.7 DMA Controller (DMAC0-DMA3)1767.3.2.8 UART Modules (UART0, UART1, and UART2)1767.3.2.9 I2C Module1777.3.2.10 Queued Serial Peripheral Interface (QSPI)1777.3.2.11 DMA Timers (DMAT0-DMAT3)1777.3.2.12 Interrupt Controllers (INTC0, INTC1)1787.3.2.13 Fast Ethernet Controller (FEC)1787.3.2.14 I/O Ports1787.3.2.15 Reset Controller1787.3.2.16 Chip Configuration Module1797.3.2.17 Clock Module1797.3.2.18 Edge Port1807.3.2.19 Watchdog Timer1807.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)1807.3.2.21 Queued Analog-to-Digital Converter (QADC)1807.3.2.22 General Purpose Timers (GPTA and GPTB)1817.3.2.23 FlexCAN1817.3.2.24 ColdFire Flash Module1837.3.2.25 BDM1847.3.2.26 JTAG1847.3.3 Summary of Peripheral State During Low-Power Modes184Table 7-7. CPU and Peripherals in Low-Power Modes (continued)184Chapter 8 System Control Module (SCM)1878.1 Overview1878.2 Features1878.3 Memory Map and Register Definition188Table 8-1. SCM Register Map1888.4 Register Descriptions1898.4.1 Internal Peripheral System Base Address Register (IPSBAR)189Figure 8-1. IPS Base Address Register (IPSBAR)190Table 8-2. IPSBAR Field Description1908.4.2 Memory Base Address Register (RAMBAR)190Figure 8-2. Memory Base Address Register (RAMBAR)191Table 8-3. RAMBAR Field Description1918.4.3 Core Reset Status Register (CRSR)192Figure 8-3. Core Reset Status Register (CRSR)192Table 8-4. CRSR Field Descriptions1928.4.4 Core Watchdog Control Register (CWCR)192Figure 8-4. Core Watchdog Control Register (CWCR)194Table 8-5. CWCR Field Description194Table 8-6. Core Watchdog Timer Delay1948.4.5 Core Watchdog Service Register (CWSR)195Figure 8-5. Core Watchdog Service Register (CWSR)1958.5 Internal Bus Arbitration195Figure 8-6. Arbiter Module Functions1968.5.1 Overview1978.5.2 Arbitration Algorithms1978.5.2.1 Round-Robin Mode1978.5.2.2 Fixed Mode1988.5.3 Bus Master Park Register (MPARK)198Figure 8-7. Default Bus Master Park Register (MPARK)198Table 8-7. MPARK Field Description1998.6 System Access Control Unit (SACU)2008.6.1 Overview2008.6.2 Features2008.6.3 Memory Map/Register Definition201Table 8-8. SACU Register Memory Map (continued)2018.6.3.1 Master Privilege Register (MPR)202Figure 8-8. Master Privilege Register (MPR)202Table 8-9. MPR[n] Field Descriptions2028.6.3.2 Peripheral Access Control Registers (PACR 0-PACR8)202Figure 8-9. Peripheral Access Control Register (PACRn)203Table 8-10. PACR Field Descriptions203Table 8-11. PACR ACCESSCTRL Bit Encodings203Table 8-12. Peripheral Access Control Registers (PACRs) (continued)2038.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 and GPACR1)204Figure 8-10. GPACR Register204Table 8-13. Grouped PeripheralAccess Control Register (GPACR) Field Descriptions205Table 8-14. GPACR ACCESS_CTRL Bit Encodings205Table 8-15. GPACR Address Space206Chapter 9 Clock Module2079.1 Features2079.2 Modes of Operation2079.2.1 Normal PLL Mode2079.2.2 1:1 PLL Mode2089.2.3 External Clock Mode2089.3 Low-power Mode Operation208Table 9-1. Clock Module Operation in Low-power Modes2089.4 Block Diagram209Figure 9-1. Clock Module Block Diagram209Figure 9-2. PLL Block Diagram2109.5 Signal Descriptions210Table 9-2. Signal Properties2109.5.1 EXTAL2109.5.2 XTAL2119.5.3 CLKOUT2119.5.4 CLKMOD[1:0]2119.5.5 RSTOUT2119.6 Memory Map and Registers2119.6.1 Module Memory Map211Table 9-3. Clock Module Memory Map2119.6.2 Register Descriptions2129.6.2.1 Synthesizer Control Register (SYNCR)212Figure 9-3. Synthesizer Control Register (SYNCR)212Table 9-4. SYNCR Field Descriptions (continued)2129.6.2.2 Synthesizer Status Register (SYNSR)214Figure 9-4. Synthesizer Status Register (SYNSR)214Table 9-5. SYNSR Field Descriptions (continued)215Table 9-6. System Clock Modes2169.7 Functional Description2169.7.1 System Clock Modes216Table 9-7. Clock Out and Clock In Relationships2179.7.2 Clock Operation During Reset2179.7.3 System Clock Generation2179.7.4 PLL Operation218Figure 9-5. Crystal Oscillator Example2189.7.4.1 Phase and Frequency Detector (PFD)2189.7.4.2 Charge Pump/Loop Filter219Table 9-8. Charge Pump Current and MFD in Normal Mode Operation2199.7.4.3 Voltage Control Output (VCO)2199.7.4.4 Multiplication Factor Divider (MFD)2199.7.4.5 PLL Lock Detection220Figure 9-6. Lock Detect Sequence2219.7.4.6 PLL Loss of Lock Conditions2219.7.4.7 PLL Loss of Lock Reset2219.7.4.8 Loss of Clock Detection2229.7.4.9 Loss of Clock Reset2229.7.4.10 Alternate Clock Selection222Table 9-9. Loss of Clock Summary2229.7.4.11 Loss of Clock in Stop Mode223Table 9-10. Stop Mode Operation (Sheet 5 of 5)223Chapter 10 Interrupt Controller Modules22910.1 68K/ColdFire Interrupt Architecture Overview22910.1.1 Interrupt Controller Theory of Operation231Table 10-1. Interrupt Priority Within a Level23110.1.1.1 Interrupt Recognition23110.1.1.2 Interrupt Prioritization23110.1.1.3 Interrupt Vector Determination23210.2 Memory Map233Table 10-2. Interrupt Controller Base Addresses233Table 10-3. Interrupt Controller Memory Map (continued)23310.3 Register Descriptions23410.3.1 Interrupt Pending Registers (IPRHn, IPRLn)234Figure 10-1. Interrupt Pending Register High (IPRHn)235Table 10-4. IPRHn Field Descriptions235Figure 10-2. Interrupt Pending Register Low (IPRLn)235Table 10-5. IPRLn Field Descriptions23510.3.2 Interrupt Mask Register (IMRHn, IMRLn)236Figure 10-3. Interrupt Mask Register High (IMRHn)236Table 10-6. IMRHn Field Descriptions236Figure 10-4. Interrupt Mask Register Low (IMRLn)236Table 10-7. IMRLn Field Descriptions23710.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)237Figure 10-5. Interrupt Force Register High (INTFRCHn)237Table 10-8. INTFRCHn Field Descriptions237Figure 10-6. Interrupt Force Register Low (INTFRCLn)238Table 10-9. INTFRCLn Field Descriptions23810.3.4 Interrupt Request Level Register (IRLRn)238Figure 10-7. Interrupt RequestLevel Register (IRLRn)238Table 10-10. IRQn Field Descriptions23810.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)239Figure 10-8. IACK Level and Priority Register (IACKLPRn)239Table 10-11. IACKLPRn Field Descriptions23910.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))239Figure 10-9. Interrupt Control Register (ICRnx)240Table 10-12. ICRnx Field Descriptions24010.3.6.1 Interrupt Sources240Table 10-13. Interrupt Source Assignment for INTC0 (continued)240Table 10-14. Interrupt Source Assignment for INTC124310.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)243Figure 10-10. Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)244Table 10-15. SWIACK and L1IACK-L7IACK Field Descriptions24410.4 Prioritization Between Interrupt Controllers24410.5 Low-Power Wakeup Operation245Chapter 11 Edge Port Module (EPORT)24711.1 Introduction247Figure 11-1. EPORT Block Diagram24711.2 Low-Power Mode Operation247Table 11-1. Edge Port Module Operation in Low-power Modes24811.3 Interrupt/General-Purpose I/O Pin Descriptions24811.4 Memory Map and Registers24911.4.1 Memory Map249Table 11-2. Edge Port Module Memory Map24911.4.2 Registers24911.4.2.1 EPORT Pin Assignment Register (EPPAR)250Figure 11-2. EPORT Pin Assignment Register (EPPAR)250Table 11-3. EPPAR Field Descriptions25011.4.2.2 EPORT Data Direction Register (EPDDR)250Figure 11-3. EPORT Data Direction Register (EPDDR)250Table 11-4. EPDD Field Descriptions25111.4.2.3 Edge Port Interrupt Enable Register (EPIER)251Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)251Table 11-5. EPIER Field Descriptions25111.4.2.4 Edge Port Data Register (EPDR)251Figure 11-5. EPORT Port Data Register (EPDR)251Table 11-6. EPDR Field Descriptions25211.4.2.5 Edge Port Pin Data Register (EPPDR)252Figure 11-6. EPORT Port Pin Data Register (EPPDR)252Table 11-7. EPPDR Field Descriptions25211.4.2.6 Edge Port Flag Register (EPFR)252Figure 11-7. EPORT Port Flag Register (EPFR)252Table 11-8. EPFR Field Descriptions253Chapter 12 Chip Select Module25512.1 Overview25512.2 Chip Select Module Signals255Table 12-1. Chip Select Module Signals255Table 12-2. Byte Enables/Byte Write Enable Signal Settings25612.3 Chip Select Operation25712.3.1 General Chip Select Operation257Table 12-3. Accesses by Matches in CSARs and DACRs25812.3.1.1 8-, 16-, and 32-Bit Port Sizing258Figure 12-1. Connections for External Memory Port Sizes25812.3.1.2 External Boot Chip Select Operation258Table 12-4. D[19:18] External Boot Chip Select Configuration25912.4 Chip Select Registers259Table 12-5. Chip Select Registers (continued)25912.4.1 Chip Select Module Registers26012.4.1.1 Chip Select Address Registers (CSAR0-CSAR6)260Figure 12-2. Chip Select Address Registers (CSARn)260Table 12-6. CSARn Field Description26112.4.1.2 Chip Select Mask Registers (CSMR0-CSMR6)261Figure 12-3. Chip Select Mask Registers (CSMRn)261Table 12-7. CSMRn Field Descriptions (continued)26112.4.1.3 Chip Select Control Registers (CSCR0-CSCR6)262Figure 12-4. Chip Select Control Registers (CSCRn)262Table 12-8. CSCRn Field Descriptions263Chapter 13 External Interface Module (EIM)26513.1 Features26513.2 Bus and Control Signals265Table 13-1. ColdFire Bus Signal Summary (Continued)26513.3 Bus Characteristics266Figure 13-1. Signal Relationship to CLKOUT for Non-DRAM Access26613.4 Data Transfer Operation266Figure 13-2. Connections for External Memory Port Sizes267Figure 13-3. Chip-Select Module Output Timing Diagram26713.4.1 Bus Cycle Execution267Table 13-2. Accesses by Matches in CSCRs and DACRs26813.4.2 Data Transfer Cycle States269Figure 13-4. Data Transfer State Transition Diagram269Table 13-3. Bus Cycle States (Continued)26913.4.3 Read Cycle270Figure 13-5. Read Cycle Flowchart271Figure 13-6. Basic Read Bus Cycle27113.4.4 Write Cycle272Figure 13-7. Write Cycle Flowchart272Figure 13-8. Basic Write Bus Cycle27213.4.5 Fast Termination Cycles273Figure 13-9. Read Cycle with Fast Termination273Figure 13-10. Write Cycle with Fast Termination27313.4.6 Back-to-Back Bus Cycles274Figure 13-11. Back-to-Back Bus Cycles27413.4.7 Burst Cycles27413.4.7.1 Line Transfers275Table 13-4. Allowable Line Access Patterns27513.4.7.2 Line Read Bus Cycles275Figure 13-12. Line Read Burst (2-1-1-1), External Termination275Figure 13-13. Line Read Burst (2-1-1-1), Internal Termination276Figure 13-14. Line Read Burst (3-2-2-2), External Termination276Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination27713.4.7.3 Line Write Bus Cycles277Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination277Figure 13-17. Line Write Burst (3-2-2-2) with One Wait State278Figure 13-18. Line Write Burst-Inhibited27813.5 Misaligned Operands278Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)279Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)279Chapter 14 Signal Descriptions28114.1 Overview281Figure 14-1. MCF5282 Block Diagram with Signal Interfaces282Table 14-1. MCF5282 Signal Description (Continued)283Table 14-2. MCF5282 Alphabetical Signal Index (Continued)288Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (Continued)29114.1.1 Single-Chip Mode296Table 14-4. Pin Reset States at Reset (Single-Chip Mode)29714.1.2 External Boot Mode297Table 14-5. Default Signal Functions After System Reset (External Boot Mode) (Continued)29714.2 MCF5282 External Signals29814.2.1 External Interface Module (EIM) Signals29814.2.1.1 Address Bus (A[23:0])29814.2.1.2 Data Bus (D[31:0])29814.2.1.3 Byte Strobes (BS[3:0])29814.2.1.4 Output Enable (OE)29914.2.1.5 Transfer Acknowledge (TA)29914.2.1.6 Transfer Error Acknowledge (TEA)29914.2.1.7 Read/Write (R/W)29914.2.1.8 Transfer Size(SIZ[1:0])299Table 14-6. Transfer Size Encoding30014.2.1.9 Transfer Start (TS)30014.2.1.10 Transfer In Progress (TIP)30014.2.1.11 Chip Selects (CS[6:0])30014.2.2 SDRAM Controller Signals30114.2.2.1 SDRAM Row Address Strobe (SRAS)30114.2.2.2 SDRAM Column Address Strobe (SCAS)30114.2.2.3 SDRAM Write Enable (DRAMW)30114.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])30114.2.2.5 SDRAM Clock Enable (SCKE)30114.2.3 Clock and Reset Signals30214.2.3.1 Reset In (RSTI)30214.2.3.2 Reset Out (RSTO)30214.2.3.3 EXTAL30214.2.3.4 XTAL30214.2.3.5 Clock Output (CLKOUT)30214.2.4 Chip Configuration Signals30214.2.4.1 RCON30214.2.4.2 CLKMOD[1:0]30214.2.5 External Interrupt Signals30314.2.5.1 External Interrupts (IRQ[7:1])30314.2.6 Ethernet Module Signals30314.2.6.1 Management Data (EMDIO)30314.2.6.2 Management Data Clock (EMDC)30314.2.6.3 Transmit Clock (ETXCLK)30314.2.6.4 Transmit Enable (ETXEN)30314.2.6.5 Transmit Data 0 (ETXD0)30314.2.6.6 Collision (ECOL)30414.2.6.7 Receive Clock (ERXCLK)30414.2.6.8 Receive Data Valid (ERXDV)30414.2.6.9 Receive Data 0 (ERXD0)30414.2.6.10 Carrier Receive Sense (ECRS)30414.2.6.11 Transmit Data 1-3 (ETXD[3:1])30414.2.6.12 Transmit Error (ETXER)30414.2.6.13 Receive Data 1-3 (ERXD[3:1])30514.2.6.14 Receive Error (ERXER)30514.2.7 Queued Serial Peripheral Interface (QSPI) Signals30514.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT)30514.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN)30514.2.7.3 QSPI Serial Clock (QSPI_CLK)30514.2.7.4 QSPI Chip Selects (QSPI_CS[3:0])30514.2.8 FlexCAN Signals30614.2.8.1 FlexCAN Transmit (CANTX)30614.2.8.2 FlexCAN Receive (CANRX)30614.2.9 I2C Signals30614.2.9.1 Serial Clock (SCL)30614.2.9.2 Serial Data (SDA)30614.2.10 UART Module Signals30614.2.10.1 Transmit Serial Data Output (UTXD[2:0])30614.2.10.2 Receive Serial Data Input (URXD[2:0])30714.2.10.3 Clear-to-Send (UCTS[1:0])30714.2.10.4 Request-to-Send (URTS[1:0])30714.2.11 General Purpose Timer Signals30714.2.11.1 GPTA[3:0]30714.2.11.2 GPTB[3:0]30714.2.11.3 External Clock Input (SYNCA/SYNCB)30714.2.12 DMA Timer Signals30814.2.12.1 DMA Timer 0 Input (DTIN0)30814.2.12.2 DMA Timer 0 Output (DTOUT0)30814.2.12.3 DMA Timer 1 Input (DTIN1)30814.2.12.4 DMA Timer 1 Output (DTOUT1)30814.2.12.5 DMA Timer 2 Input (DTIN2)30814.2.12.6 DMA Timer 2 Output (DTOUT2)30814.2.12.7 DMA Timer 3 Input (DTIN3)30914.2.12.8 DMA Timer 3 Output (DTOUT3)30914.2.13 Analog-to-Digital Converter Signals30914.2.13.1 QADC Analog Input (AN0/ANW)30914.2.13.2 QADC Analog Input (AN1/ANX)30914.2.13.3 QADC Analog Input (AN2/ANY)30914.2.13.4 QADC Analog Input (AN3/ANZ)30914.2.13.5 QADC Analog Input (AN52/MA0)30914.2.13.6 QADC Analog Input (AN53/MA1)31014.2.13.7 QADC Analog Input (AN55/TRIG1)31014.2.13.8 QADC Analog Input (AN56/TRIG2)31014.2.14 Debug Support Signals31014.2.14.1 JTAG_EN31014.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)31014.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS)31114.2.14.4 Development Serial Input/Test Data (DSI/TDI)31114.2.14.5 Development Serial Output/Test Data (DSO/TDO)31114.2.14.6 Test Clock (TCLK)31114.2.14.7 Debug Data (DDATA[3:0])31214.2.14.8 Processor Status Outputs (PST[3:0])312Table 14-7. Processor Status Encoding31214.2.15 Test Signals31214.2.15.1 Test (TEST)31214.2.16 Power and Reference Signals31314.2.16.1 QADC Analog Reference (VRH, VRL)31314.2.16.2 QADC Analog Supply (VDDA, VSSA)31314.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL)31314.2.16.4 QADC Positive Supply (VDDH)31314.2.16.5 Power for Flash Erase/Program (VPP)31314.2.16.6 Power and Ground for Flash Array (VDDF, VSSF)31314.2.16.7 Standby Power (VSTBY)31314.2.16.8 Positive Supply (VDD)31314.2.16.9 Ground (VSS)313Chapter 15 Synchronous DRAM Controller Module31515.1 Overview31515.1.1 Definitions31515.1.2 Block Diagram and Major Components316Figure 15-1. Synchronous DRAM Controller Block Diagram31615.2 SDRAM Controller Operation317Table 15-1. SDRAM Commands31715.2.1 DRAM Controller Signals318Table 15-2. Synchronous DRAM Signal Connections31815.2.2 Memory Map for SDRAMC Registers318Table 15-3. DRAM Controller Registers31815.2.2.1 DRAM Control Register (DCR)319Figure 15-2. DRAM Control Register (DCR)319Table 15-4. DCR Field Descriptions31915.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)320Figure 15-3. DRAM Address and Control Register (DACRn)320Table 15-5. DACRn Field Descriptions (continued)32015.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)322Figure 15-4. DRAM Controller Mask Registers (DMRn)322Table 15-6. DMRn Field Descriptions32215.2.3 General Synchronous Operation Guidelines32315.2.3.1 Address Multiplexing323Table 15-7. Generic Address Multiplexing Scheme323Table 15-8. MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)324Table 15-9. MCF5282 to SDRAM Interface (8-Bit Port,10-Column Address Lines)324Table 15-10. MCF5282 to SDRAM Interface (8-Bit Port,11-Column Address Lines)324Table 15-11. MCF5282 to SDRAM Interface (8-Bit Port,12-Column Address Lines)324Table 15-12. MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)324Table 15-13. MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)325Table 15-14. MCF5282 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)325Table 15-15. MCF5282 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)325Table 15-16. MCF5282 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)325Table 15-17. MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)325Table 15-18. MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)326Table 15-19. MCF5282 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)326Table 15-20. MCF5282 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)326Table 15-21. MCF5282 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)326Table 15-22. MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)326Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)32715.2.3.2 SDRAM Byte Strobe Connections327Figure 15-5. Connections for External Memory Port Sizes32715.2.3.3 Interfacing Example327Table 15-24. SDRAM Hardware Connections32715.2.3.4 Burst Page Mode327Figure 15-6. Burst Read SDRAM Access328Figure 15-7. Burst Write SDRAM Access32915.2.3.5 Auto-Refresh Operation329Figure 15-8. Auto-Refresh Operation33015.2.3.6 Self-Refresh Operation330Figure 15-9. Self-Refresh Operation33115.2.4 Initialization Sequence33115.2.4.1 Mode Register Settings332Figure 15-10. Mode Register Set (mrs) Command33315.3 SDRAM Example333Table 15-25. SDRAM Example Specifications33315.3.1 SDRAM Interface Configuration334Table 15-26. SDRAM Hardware Connections33415.3.2 DCR Initialization334Figure 15-11. Initialization Values for DCR334Table 15-27. DCR Initialization Values33415.3.3 DACR Initialization334Figure 15-12. SDRAM Configuration335Figure 15-13. DACR Register Configuration335Table 15-28. DACR Initialization Values (continued)33515.3.4 DMR Initialization336Figure 15-14. DMR0 Register336Table 15-29. DMR0 Initialization Values (continued)33615.3.5 Mode Register Initialization337Table 15-30. Mode Register Initialization337Table 15-31. Mode Register Mapping to MCF5282 A[31:0]33715.3.6 Initialization Code338Chapter 16 DMA Controller Module34116.1 Overview341Figure 16-1. DMA Signal Diagram34216.1.1 DMA Module Features34216.2 DMA Request Control (DMAREQC)343Figure 16-2. DMA Request Control Register (DMAREQC)343Table 16-1. DMAREQC Field Description34316.3 DMA Transfer Overview344Figure 16-3. Dual-Address Transfer34416.4 DMA Controller Module Programming Model345Table 16-2. Memory Map for DMA Controller Module Registers34516.4.1 Source Address Registers (SAR0-SAR3)346Figure 16-4. Source Address Registers (SARn)34616.4.2 Destination Address Registers (DAR0-DAR3)346Figure 16-5. Destination Address Registers (DARn)34616.4.3 Byte Count Registers (BCR0-BCR3)347Figure 16-6. Byte Count Registers (BCRn)-BCR24BIT = 1347Figure 16-7. Byte Count Registers (BCRn)-BCR24BIT = 034716.4.4 DMA Control Registers (DCR0-DCR3)348Figure 16-8. DMA Control Registers (DCRn)348Table 16-3. DCRn Field Descriptions (continued)34816.4.5 DMA Status Registers (DSR0-DSR3)350Figure 16-9. DMA Status Registers (DSRn)350Table 16-4. DSRn Field Descriptions (continued)35016.5 DMA Controller Module Functional Description35116.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)35116.5.2 Data Transfer Modes35216.5.2.1 Dual-Address Transfers35216.5.3 Channel Initialization and Startup35316.5.3.1 Channel Prioritization35316.5.3.2 Programming the DMA Controller Module35316.5.4 Data Transfer35416.5.4.1 Auto-Alignment35416.5.4.2 Bandwidth Control35516.5.5 Termination355Chapter 17 Fast Ethernet Controller (FEC)35717.1 Overview35717.1.1 Features35717.2 Modes of Operation35817.2.1 Full and Half Duplex Operation35817.2.2 Interface Options35817.2.2.1 10 Mbps and 100 Mbps MII Interface35817.2.2.2 10 Mpbs 7-Wire Interface Operation35917.2.3 Address Recognition Options35917.2.4 Internal Loopback35917.3 FEC Top-Level Functional Diagram360Figure 17-1. FEC Block Diagram36017.4 Functional Description36117.4.1 Initialization Sequence36217.4.1.1 Hardware Controlled Initialization362Table 17-1. ECR[ETHER_EN] De-Assertion Effect on FEC36217.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])362Table 17-2. User Initialization (Before ECR[ETHER_EN]) (continued)362Table 17-3. FEC User Initialization (Before ECR[ETHER_EN])36317.4.3 Microcontroller Initialization363Table 17-4. Microcontroller Initialization36317.4.4 User Initialization (After Asserting ECR[ETHER_EN])36317.4.5 Network Interface Options364Table 17-5. MII Mode364Table 17-6. 7-Wire Mode Configuration36417.4.6 FEC Frame Transmission36517.4.7 FEC Frame Reception36617.4.8 Ethernet Address Recognition367Figure 17-2. Ethernet Address Recognition-Receive Block Decisions368Figure 17-3. Ethernet Address Recognitionq-Microcode Decisions36917.4.9 Hash Algorithm369Table 17-7. Destination Address to 6-Bit Hash (continued)37017.4.10 Full Duplex Flow Control372Table 17-8. PAUSE Frame Field Specification37217.4.11 Inter-Packet Gap (IPG) Time37317.4.12 Collision Handling37317.4.13 Internal and External Loopback37317.4.14 Ethernet Error-Handling Procedure37417.4.14.1 Transmission Errors37417.4.14.2 Reception Errors37517.5 Programming Model37617.5.1 Top Level Module Memory Map376Table 17-9. Module Memory Map37617.5.2 Detailed Memory Map (Control/Status Registers)376Table 17-10. FEC Register Memory Map (continued)37617.5.3 MIB Block Counters Memory Map377Table 17-11. MIB Counters Memory Map (continued)37817.5.4 Registers37917.5.4.1 Ethernet Interrupt Event Register (EIR)379Figure 17-4. Ethernet Interrupt Event Register (EIR)380Table 17-12. EIR Field Descriptions (continued)38017.5.4.2 Interrupt Mask Register (EIMR)382Figure 17-5. Interrupt Mask Register (EIMR)382Table 17-13. EIMR Field Descriptions38217.5.4.3 Receive Descriptor Active Register (RDAR)382Figure 17-6. Receive Descriptor Active Register (RDAR)383Table 17-14. RDAR Field Descriptions38317.5.4.4 Transmit Descriptor Active Register (TDAR)383Figure 17-7. Transmit Descriptor Active Register (TDAR)384Table 17-15. TDAR Field Descriptions38417.5.4.5 Ethernet Control Register (ECR)384Figure 17-8. Ethernet Control Register (ECR)384Table 17-16. ECR Field Descriptions38517.5.4.6 MII Management Frame Register (MMFR)385Figure 17-9. MII Management Frame Register (MMFR)385Table 17-17. MMFR Field Descriptions38617.5.4.7 MII Speed Control Register (MSCR)387Figure 17-10. MII Speed Control Register (MSCR)387Table 17-18. MSCR Field Descriptions387Table 17-19. Programming Examples for MSCR38817.5.4.8 MIB Control Register (MIBC)388Figure 17-11. MIB Control Register (MIBC)388Table 17-20. MIBC Field Descriptions38817.5.4.9 Receive Control Register (RCR)389Figure 17-12. Receive Control Register (RCR)389Table 17-21. RCR Field Descriptions (continued)38917.5.4.10 Transmit Control Register (TCR)390Figure 17-13. Transmit Control Register (TCR)390Table 17-22. TCR Field Descriptions39117.5.4.11 Physical Address Low Register (PALR)391Figure 17-14. Physical Address Low Register (PALR)392Table 17-23. PALR Field Descriptions39217.5.4.12 Physical Address High Register (PAUR)392Figure 17-15. Physical Address High Register (PAUR)392Table 17-24. PAUR Field Descriptions39317.5.4.13 Opcode/Pause Duration Register (OPD)393Figure 17-16. Opcode/Pause Duration Register (OPD)393Table 17-25. OPD Field Descriptions39317.5.4.14 Descriptor Individual Upper Address Register (IAUR)393Figure 17-17. Descriptor Individual Upper Address Register (IAUR)394Table 17-26. IAUR Field Descriptions39417.5.4.15 Descriptor Individual Lower Address (IALR)394Figure 17-18. Descriptor Individual Lower Address Register (IALR)394Table 17-27. IALR Field Descriptions39517.5.4.16 Descriptor Group Upper Address (GAUR)395Figure 17-19. Descriptor Group Upper Address Register (GAUR)395Table 17-28. GAUR Field Descriptions39517.5.4.17 Descriptor Group Lower Address (GALR)395Figure 17-20. Descriptor Group Lower Address Register (GALR)396Table 17-29. GALR Field Descriptions39617.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)396Figure 17-21. FIFO Transmit FIFO Watermark Register (TFWR)396Table 17-30. TFWR Field Descriptions39717.5.4.19 FIFO Receive Bound Register (FRBR)397Figure 17-22. FIFO Receive Bound Register (FRBR)397Table 17-31. FRBR Field Descriptions39717.5.4.20 FIFO Receive Start Register (FRSR)398Figure 17-23. FIFO Receive Start Register (FRSR)398Table 17-32. FRSR Field Descriptions39817.5.4.21 Receive Descriptor Ring Start (ERDSR)398Figure 17-24. Receive Descriptor Ring Start Register (ERDSR)399Table 17-33. ERDSR Field Descriptions39917.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR)399Figure 17-25. Transmit Buffer Descriptor Ring Start Register (ETDSR)399Table 17-34. ETDSR Field Descriptions40017.5.4.23 Receive Buffer Size Register (EMRBR)400Figure 17-26. Receive Buffer Size Register (EMRBR)400Table 17-35. EMRBR Field Descriptions40017.6 Buffer Descriptors40117.6.1 Driver/DMA Operation with Buffer Descriptors40117.6.1.1 Driver/DMA Operation with Transmit BDs40117.6.1.2 Driver/DMA Operation with Receive BDs40217.6.2 Ethernet Receive Buffer Descriptor (RxBD)403Figure 17-27. Receive Buffer Descriptor (RxBD)403Table 17-36. Receive Buffer Descriptor Field Definitions (continued)40417.6.3 Ethernet Transmit Buffer Descriptor (TxBD)405Figure 17-28. Transmit Buffer Descriptor (TxBD)406Table 17-37. Transmit Buffer Descriptor Field Definitions (continued)406Chapter 18 Watchdog Timer Module40918.1 Introduction40918.2 Low-Power Mode Operation409Table 18-1. Watchdog Module Operation in Low-power Modes40918.3 Block Diagram410Figure 18-1. Watchdog Timer Block Diagram41018.4 Signals41018.5 Memory Map and Registers41018.5.1 Memory Map410Table 18-2. Watchdog Timer Module Memory Map41118.5.2 Registers41118.5.2.1 Watchdog Control Register (WCR)411Figure 18-2. Watchdog Control Register (WCR)411Table 18-3. WCR Field Descriptions41218.5.2.2 Watchdog Modulus Register (WMR)412Figure 18-3. Watchdog Modulus Register (WMR)412Table 18-4. WMR Field Descriptions41318.5.2.3 Watchdog Count Register (WCNTR)413Figure 18-4. Watchdog Count Register (WCNTR)413Table 18-5. WCNTR Field Descriptions41318.5.2.4 Watchdog Service Register (WSR)413Figure 18-5. Watchdog Service Register (WSR)414Chapter 19 Programmable Interrupt Timer Modules (PIT0-PIT3)41519.1 Overview41519.2 Block Diagram415Figure 19-1. PIT Block Diagram41519.3 Low-Power Mode Operation416Table 19-1. PIT Module Operation in Low-power Modes41619.4 Signals41619.5 Memory Map and Registers41719.5.1 Memory Map417Table 19-2. Programmable Interrupt Timer Modules Memory Map41719.5.2 Registers41719.5.2.1 PIT Control and Status Register (PCSR)418Figure 19-2. PIT Control and Status Register (PCSR)418Table 19-3. PCSR Field Descriptions (continued)41819.5.2.2 PIT Modulus Register (PMR)419Figure 19-3. PIT Modulus Register (PMR)42019.5.2.3 PIT Count Register (PCNTR)420Figure 19-4. PIT Count Register (PCNTR)42019.6 Functional Description42019.6.1 Set-and-Forget Timer Operation420Figure 19-5. Counter Reloading from the Modulus Latch42119.6.2 Free-Running Timer Operation421Figure 19-6. Counter in Free-Running Mode42119.6.3 Timeout Specifications42119.7 Interrupt Operation422Table 19-4. PIT Interrupt Requests422Chapter 20 General Purpose Timer Modules (GPTA and GPTB)42320.1 Features42320.2 Block Diagram424Figure 20-1. GPT Block Diagram42420.3 Low-Power Mode Operation425Table 20-1. Watchdog Module Operation in Low-power Modes42520.4 Signal Description425Table 20-2. Signal Properties42520.4.1 GPTn[2:0]42520.4.2 GPTn342620.4.3 SYNCn42620.5 Memory Map and Registers426Table 20-3. GPT Modules Memory Map (continued)42620.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)427Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)427Table 20-4. GPTIOS Field Descriptions42820.5.2 GPT Compare Force Register (GPCFORC)428Figure 20-3. GPT Input Compare Force Register (GPCFORC)428Table 20-5. GPTCFORC Field Descriptions42820.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)428Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M)428Table 20-6. GPTOC3M Field Descriptions42920.5.4 GPT Output Compare 3 Data Register (GPTOC3D)429Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D)429Table 20-7. GPTOC3D Field Descriptions42920.5.5 GPT Counter Register (GPTCNT)429Figure 20-6. GPT Counter Register (GPTCNT)429Table 20-8. GPTCNT Field Descriptions43020.5.6 GPT System Control Register 1 (GPTSCR1)430Figure 20-7. GPT System Control Register 1 (GPTSCR1)430Table 20-9. GPTSCR1 Field Descriptions430Figure 20-8. Fast Clear Flag Logic43120.5.7 GPT Toggle-On-Overflow Register (GPTTOV)431Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV)431Table 20-10. GPTTOV Field Description43120.5.8 GPT Control Register 1 (GPTCTL1)431Figure 20-10. GPT Control Register 1 (GPTCTL1)431Table 20-11. GPTCL1 Field Descriptions43220.5.9 GPT Control Register 2 (GPTCTL2)432Figure 20-11. GPT Control Register 2 (GPTCTL2)432Table 20-12. GPTLCTL2 Field Descriptions43220.5.10 GPT Interrupt Enable Register (GPTIE)432Figure 20-12. GPT Interrupt Enable Register (GPTIE)432Table 20-13. GPTIE Field Descriptions43320.5.11 GPT System Control Register 2 (GPTSCR2)433Figure 20-13. GPT System Control Register 2 (GPTSCR2)433Table 20-14. GPTSCR2 Field Descriptions43320.5.12 GPT Flag Register 1 (GPTFLG1)434Figure 20-14. GPT Flag Register 1 (GPTFLG1)434Table 20-15. GPTFLG1 Field Descriptions43420.5.13 GPT Flag Register 2 (GPTFLG2)434Figure 20-15. GPT Flag Register 2 (GPTFLG2)434Table 20-16. GPTFLG2 Field Descriptions43420.5.14 GPT Channel Registers (GPTCn)435Figure 20-16. GPT Channel[0:3] Register (GPTCn)435Table 20-17. GPTCn Field Descriptions43520.5.15 Pulse Accumulator Control Register (GPTPACTL)435Figure 20-17. Pulse Accumulator Control Register (GPTPACTL)435Table 20-18. GPTPACTL Field Descriptions (continued)43520.5.16 Pulse Accumulator Flag Register (GPTPAFLG)436Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG)436Table 20-19. GPTPAFLG Field Descriptions43720.5.17 Pulse Accumulator Counter Register (GPTPACNT)437Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)437Table 20-20. GPTPACR Field Descriptions43720.5.18 GPT Port Data Register (GPTPORT)438Figure 20-20. GPT Port Data Register (GPTPORT)438Table 20-21. GPTPORT Field Descriptions43820.5.19 GPT Port Data Direction Register (GPTDDR)438Figure 20-21. GPT Port Data Direction Register (GPTDDR)438Table 20-22. GPTDDR Field Descriptions43820.6 Functional Description43920.6.1 Prescaler43920.6.2 Input Capture43920.6.3 Output Compare43920.6.4 Pulse Accumulator44020.6.5 Event Counter Mode44020.6.6 Gated Time Accumulation Mode441Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic44120.6.7 General-Purpose I/O Ports441Table 20-23. GPT Settings and Pin Functions (continued)44220.7 Reset44320.8 Interrupts443Table 20-24. GPT Interrupt Requests44320.8.1 GPT Channel Interrupts (CnF)44420.8.2 Pulse Accumulator Overflow (PAOVF)44420.8.3 Pulse Accumulator Input (PAIF)44420.8.4 Timer Overflow (TOF)444Chapter 21 DMA Timers (DTIM0-DTIM3)44721.1 Overview447Figure 21-1. DMA Timer Block Diagram44821.1.1 Key Features44821.2 DMA Timer Programming Model44821.2.1 Prescaler44821.2.2 Capture Mode44921.2.3 Reference Compare44921.2.4 Output Mode44921.2.5 Memory Map449Table 21-1. DMA Timer Module Memory Map (continued)44921.2.6 DMA Timer Mode Registers (DTMRn)450Figure 21-2. DTMRn Bit Definitions450Table 21-2. DTMRn Field Descriptions45121.2.7 DMA Timer Extended Mode Registers (DTXMRn)451Figure 21-3. DTXMRn Bit Definitions451Table 21-3. DTXMRn Field Descriptions45221.2.8 DMA Timer Event Registers (DTERn)452Figure 21-4. DTERn Bit Definitions452Table 21-4. DTERn Field Descriptions45321.2.9 DMA Timer Reference Registers (DTRRn)453Figure 21-5. DTRRn Bit Definitions45321.2.10 DMA Timer Capture Registers (DTCRn)453Figure 21-6. DTCRn Bit Definitions45421.2.11 DMA Timer Counters (DTCNn)454Figure 21-7. DTCNn Bit Definitions45421.3 Using the DMA Timer Modules45421.3.1 Code Example45521.3.2 Calculating Time-Out Values456Chapter 22 Queued Serial Peripheral Interface (QSPI) Module45722.1 Overview45722.2 Features45722.3 Module Description45722.3.1 Interface and Signals458Figure 22-1. QSPI Block Diagram458Table 22-1. QSPI Input and Output Signals and Functions45922.3.2 Internal Bus Interface45922.4 Operation45922.4.1 QSPI RAM460Figure 22-2. QSPI RAM Model46122.4.1.1 Receive RAM46122.4.1.2 Transmit RAM46222.4.1.3 Command RAM46222.4.2 Baud Rate Selection462Table 22-2. QSPI_CLK Frequency as Function of System Clock and Baud Rate46322.4.3 Transfer Delays46322.4.4 Transfer Length46422.4.5 Data Transfer46422.5 Programming Model465Table 22-3. QSPI Registers46522.5.1 QSPI Mode Register (QMR)466Figure 22-3. QSPI Mode Register (QMR)466Table 22-4. QMR Field Descriptions (continued)466Figure 22-4. QSPI Clocking and Data Transfer Example46722.5.2 QSPI Delay Register (QDLYR)467Figure 22-5. QSPI Delay Register (QDLYR)467Table 22-5. QDLYR Field Descriptions46822.5.3 QSPI Wrap Register (QWR)468Figure 22-6. QSPI Wrap Register (QWR)468Table 22-6. QWR Field Descriptions46822.5.4 QSPI Interrupt Register (QIR)469Figure 22-7. QSPI Interrupt Register (QIR)469Table 22-7. QIR Field Descriptions46922.5.5 QSPI Address Register (QAR)470Figure 22-8. QSPI Address Register47022.5.6 QSPI Data Register (QDR)470Figure 22-9. QSPI Data Register (QDR)47022.5.7 Command RAM Registers (QCR0-QCR15)471Figure 22-10. Command RAM Registers (QCR0-QCR15)471Table 22-8. QCR0-QCR15 Field Descriptions471Figure 22-11. QSPI Timing47222.5.8 Programming Example472Chapter 23 UART Modules47523.1 Overview475Figure 23-1. Simplified Block Diagram47523.2 Serial Module Overview47623.3 Register Descriptions477Table 23-1. UART Module Memory Map (continued)47723.3.1 UART Mode Registers 1 (UMR1n)478Figure 23-2. UART Mode Registers 1 (UMR1n)478Table 23-2. UMR1n Field Descriptions47923.3.2 UART Mode Register 2 (UMR2n)480Figure 23-3. UART Mode Register 2 (UMR2n)480Table 23-3. UMR2n Field Descriptions (continued)48023.3.3 UART Status Registers (USRn)481Figure 23-4. UART Status Register (USRn)481Table 23-4. USRn Field Descriptions (continued)48123.3.4 UART Clock Select Registers (UCSRn)482Figure 23-5. UART Clock Select Register (UCSRn)482Table 23-5. UCSRn Field Descriptions48323.3.5 UART Command Registers (UCRn)483Figure 23-6. UART Command Register (UCRn)483Table 23-6. UCRn Field Descriptions (continued)48423.3.6 UART Receive Buffers (URBn)485Figure 23-7. UART Receive Buffer (URBn)48523.3.7 UART Transmit Buffers (UTBn)485Figure 23-8. UART Transmit Buffer (UTBn)48623.3.8 UART Input Port Change Registers (UIPCRn)486Figure 23-9. UART Input Port Change Register (UIPCRn)486Table 23-7. UIPCRn Field Descriptions48623.3.9 UART Auxiliary Control Register (UACRn)487Figure 23-10. UART Auxiliary Control Register (UACRn)487Table 23-8. UACRn Field Descriptions48723.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)487Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)487Table 23-9. UISRn/UIMRn Field Descriptions48823.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)488Figure 23-12. UART Baud Rate Generator Register (UBG1n)488Figure 23-13. UART Baud Rate Generator Register (UBG2n)48823.3.12 UART Input Port Register (UIPn)489Figure 23-14. UART Input Port Register (UIPn)489Table 23-10. UIPn Field Descriptions48923.3.13 UART Output Port Command Registers (UOP1n/UOP0n)489Figure 23-15. UART Output Port Command Registers (UOP1n/UOP0n)489Table 23-11. UOP1/UOP0 Field Descriptions49023.4 UART Module Signal Definitions491Figure 23-16. UART Block Diagram Showing External and Internal Interface Signals491Table 23-12. UART Module Signals492Figure 23-17. UART/RS-232 Interface49223.5 Operation49223.5.1 Transmitter/Receiver Clock Source49223.5.1.1 Programmable Divider492Figure 23-18. Clocking Source Diagram49323.5.1.2 Calculating Baud Rates49323.5.2 Transmitter and Receiver Operating Modes494Figure 23-19. Transmitter and Receiver Functional Diagram49423.5.2.1 Transmitter494Figure 23-20. Transmitter Timing Diagram49623.5.2.2 Receiver496Figure 23-21. Receiver Timing49723.5.2.3 FIFO Stack49723.5.3 Looping Modes49923.5.3.1 Automatic Echo Mode499Figure 23-22. Automatic Echo49923.5.3.2 Local Loop-Back Mode499Figure 23-23. Local Loop-Back49923.5.3.3 Remote Loop-Back Mode500Figure 23-24. Remote Loop-Back50023.5.4 Multidrop Mode500Figure 23-25. Multidrop Mode Timing Diagram50123.5.5 Bus Operation50223.5.5.1 Read Cycles50223.5.5.2 Write Cycles50223.5.6 Programming50223.5.6.1 Interrupt and DMA Request Initialization503Table 23-13. UART Interrupts503Table 23-14. UART DMA Requests50423.5.6.2 UART Module Initialization Sequence504Table 23-15. UART Module Initialization Sequence504Figure 23-26. UART Mode Programming Flowchart (Sheet 5 of 5)505Chapter 24 I2C Interface51124.1 Overview51124.2 Interface Features511Figure 24-1. I2C Module Block Diagram51224.3 I2C System Configuration51324.4 I2C Protocol513Figure 24-2. I2C Standard Communication Protocol513Figure 24-3. Repeated START51424.4.1 Arbitration Procedure51424.4.2 Clock Synchronization515Figure 24-4. Synchronized Clock SCL51524.4.3 Handshaking51524.4.4 Clock Stretching51524.5 Programming Model516Table 24-1. I2C Interface Memory Map51624.5.1 I2C Address Register (I2ADR)516Figure 24-5. I2C Address Register (I2ADR)516Table 24-2. I2ADR Field Descriptions51624.5.2 I2C Frequency Divider Register (I2FDR)517Figure 24-6. I2C Frequency Divider Register (I2FDR)517Table 24-3. I2FDR Field Descriptions51724.5.3 I2C Control Register (I2CR)518Figure 24-7. I2C Control Register (I2CR)518Table 24-4. I2CR Field Descriptions51824.5.4 I2C Status Register (I2SR)519Figure 24-8. I2CR Status Register (I2SR)519Table 24-5. I2SR Field Descriptions (continued)51924.5.5 I2C Data I/O Register (I2DR)520Figure 24-9. I2C Data I/O Register (I2DR)52024.6 I2C Programming Examples52024.6.1 Initialization Sequence52024.6.2 Generation of START52124.6.3 Post-Transfer Software Response52124.6.4 Generation of STOP52224.6.5 Generation of Repeated START52324.6.6 Slave Mode52324.6.7 Arbitration Lost524Figure 24-10. Flow-Chart of Typical I2C Interrupt Routine525Chapter 25 FlexCAN52725.1 Features527Figure 25-1. FlexCAN Block Diagram and Pinout52825.1.1 FlexCAN Memory Map529Table 25-1. FlexCAN Memory Map52925.1.2 External Signals52925.2 The CAN System530Figure 25-2. Typical CAN system53025.3 Message Buffers53025.3.1 Message Buffer Structure530Figure 25-3. Extended ID Message Buffer Structure531Figure 25-4. Standard ID Message Buffer Structure53125.3.1.1 Common Fields for Extended and Standard Format Frames531Table 25-2. Common Extended/Standard Format Frames532Table 25-3. Message Buffer Codes for Receive Buffers532Table 25-4. Message Buffer Codes for Transmit Buffers53225.3.1.2 Fields for Extended Format Frames533Table 25-5. Extended Format Frames53325.3.1.3 Fields for Standard Format Frames533Table 25-6. Standard Format Frames53325.3.2 Message Buffer Memory Map533Figure 25-5. FlexCAN Memory Map53425.4 Functional Overview53425.4.1 Transmit Process53525.4.2 Receive Process53525.4.2.1 Self-Received Frames53625.4.3 Message Buffer Handling53625.4.3.1 Serial Message Buffers (SMBs)53725.4.3.2 Transmit Message Buffer Deactivation53725.4.3.3 Receive Message Buffer Deactivation53725.4.3.4 Locking and Releasing Message Buffers53825.4.4 Remote Frames53825.4.5 Overload Frames53925.4.6 Time Stamp53925.4.7 Listen-Only Mode53925.4.8 Bit Timing540Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock54025.4.8.1 Configuring the FlexCAN Bit Timing54025.4.9 FlexCAN Error Counters54125.4.10 FlexCAN Initialization Sequence54225.4.11 Special Operating Modes54325.4.11.1 Debug Mode54325.4.11.2 Low-Power Stop Mode for Power Saving54325.4.11.3 Auto-Power Save Mode54525.4.12 Interrupts54525.5 Programmer’s Model54625.5.1 CAN Module Configuration Register (CANMCR)546Figure 25-6. CAN Module Configuration Register (CANMCR)546Table 25-8. CANMCR Field Descriptions (continued)54725.5.2 FlexCAN Control Register 0 (CANCTRL0)548Figure 25-7. FlexCAN Control Register 0 (CANCTRL0)548Table 25-9. CANCTRL0 Field Descriptions549Table 25-10. Transmit Pin Configuration54925.5.3 FlexCAN Control Register 1 (CANCTRL1)549Figure 25-8. FlexCAN Control Register 1 (CANCTRL1)549Table 25-11. CANCTRL1 Field Descriptions55025.5.4 Prescaler Divide Register (PRESDIV)550Figure 25-9. Prescaler Divide Register (PRESDIV)550Table 25-12. PRESDIV Field Descriptions55125.5.5 FlexCAN Control Register 2 (CANCTRL2)551Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)551Table 25-13. CANCTRL2 Field Descriptions55125.5.6 Free Running Timer (TIMER)552Figure 25-11. Free Running Timer (TIMER)552Table 25-14. TIMER Field Descriptions55225.5.7 Rx Mask Registers552Table 25-15. Mask examples for Normal/Extended Messages (continued)55225.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK)553Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)553Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions55425.5.8 FlexCAN Error and Status Register (ESTAT)554Figure 25-13. FlexCAN Error and Status Register (ESTAT)554Table 25-17. ESTAT Field Descriptions (continued)55525.5.9 Interrupt Mask Register (IMASK)556Figure 25-14. Interrupt Mask Register (IMASK)556Table 25-18. IMASK Field Descriptions55725.5.10 Interrupt Flag Register (IFLAG)557Figure 25-15. Interrupt Flag Register (IFLAG)557Table 25-19. IFLAG Field Descriptions55725.5.11 FlexCAN Receive Error Counter (RXECTR)558Figure 25-16. FlexCAN Receive Error Counter (RXECTR)558Table 25-20. RXECTR Field Descriptions55825.5.12 FlexCAN Transmit Error Counter (TXECTR)558Figure 25-17. FlexCAN Transmit Error Counter (TXECTR)558Table 25-21. TXECTR Field Descriptions558Chapter 26 General Purpose I/O Module55926.1 Introduction559Figure 26-1. MCF5282 Ports Module Block Diagram56026.1.1 Overview56126.1.2 Features56126.1.3 Modes of Operation56126.2 External Signal Description562Table 26-1. MCF5282 Ports External Signals (continued)56226.3 Memory Map/Register Definition56426.3.1 Register Overview564Table 26-2. MCF5282 Ports Module Memory Map (continued)56426.3.2 Register Descriptions56626.3.2.1 Port Output Data Registers (PORTn)566Figure 26-2. Port Output Data Registers (8-bit)566Figure 26-3. Port Output Data Register (7-bit)566Figure 26-4. Port Output Data Registers (6-bit)566Figure 26-5. Port Output Data Registers (4-bit)567Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions56726.3.2.2 Port Data Direction Registers (DDRn)567Figure 26-6. Port Data Direction Registers (8-bit)567Figure 26-7. Port Data Direction Register (7-bit)568Figure 26-8. Port Data Direction Registers (6-bit)568Figure 26-9. Port Data Direction Registers (4-bit)568Table 26-4. DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions56826.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)569Figure 26-10. Port Pin Data/Set Data Registers (8-bit)569Figure 26-11. Port Pin Data/Set Data Register (7-bit)569Figure 26-12. Port Pin Data/Set Data Registers (6-bit)569Figure 26-13. Port Pin Data/Set Data Registers (4-bit)570Table 26-5. PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions57026.3.2.4 Port Clear Output Data Registers (CLRn)570Figure 26-14. Port Clear Output Data Registers (8-bit)570Figure 26-15. Port Clear Output Data Register (7-bit)571Figure 26-16. Port Clear Output Data Registers (6-bit)571Figure 26-17. Port Clear Output Data Registers (4-bit)571Table 26-6. CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions57126.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)572Figure 26-18. Port B/C/D Pin Assignment Register (PBCDPAR)572Table 26-7. PBCDPAR Field Descriptions572Table 26-8. Reset Values for PBCDPAR Bits57226.3.2.6 Port E Pin Assignment Register (PEPAR)573Figure 26-19. Port E Pin Assignment Register (PEPAR)573Table 26-9. PEPAR Field Descriptions (continued)573Table 26-10. Reset Values for PEPAR Bits and Fields57426.3.2.7 Port F Pin Assignment Register (PFPAR)575Figure 26-20. Port F Pin Assignment Register (PFPAR)575Table 26-11. PFPAR Field Descriptions57526.3.2.8 Port J Pin Assignment Register (PJPAR)576Figure 26-21. Port J Pin Assignment Register (PJPAR)576Table 26-12. PJPAR Field Descriptions57626.3.2.9 Port SD Pin Assignment Register (PSDPAR)577Figure 26-22. Port SD Pin Assignment Register (PSDPAR)577Table 26-13. PSDPAR Field Descriptions57726.3.2.10 Port AS Pin Assignment Register (PASPAR)577Figure 26-23. Port AS Pin Assignment Register (PASPAR)577Table 26-14. PASPAR Field Descriptions57826.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR)578Figure 26-24. Port EH/EL Pin Assignment Register (PEHLPAR)578Table 26-15. PEHLPAR Field Descriptions57926.3.2.12 Port QS Pin Assignment Register (PQSPAR)579Figure 26-25. Port QS Pin Assignment Register (PQSPAR)579Table 26-16. PQSPAR Field Description (continued)57926.3.2.13 Port TC Pin Assignment Register (PTCPAR)580Figure 26-26. Port TC Pin Assignment Register (PTCPAR)580Table 26-17. PTCPAR Field Descriptions (continued)58026.3.2.14 Port TD Pin Assignment Register (PTDPAR)581Figure 26-27. Port TD Pin Assignment Register (PTDPAR)581Table 26-18. PTDPAR Field Descriptions (continued)58126.3.2.15 Port UA Pin Assignment Register (PUAPAR)582Figure 26-28. Port UA Pin Assignment Register (PUAPAR)582Table 26-19. PUAPAR Field Descriptions58226.4 Functional Description58326.4.1 Overview58326.4.2 Port Digital I/O Timing583Figure 26-29. Digital Input Timing583Figure 26-30. Digital Output Timing58426.5 Initialization/Application Information584Chapter 27 Queued Analog-to-Digital Converter (QADC)58527.1 Features58527.2 Block Diagram586Figure 27-1. QADC Block Diagram58627.3 Modes of Operation58727.3.1 Debug Mode58727.3.2 Stop Mode58727.4 Signals58827.4.1 Port QA Signal Functions58827.4.1.1 Port QA Analog Input Signals588Figure 27-2. QADC Input and Output Signals58927.4.1.2 Port QA Digital Input/Output Signals58927.4.2 Port QB Signal Functions58927.4.2.1 Port QB Analog Input Signals58927.4.2.2 Port QB Digital I/O Signals59027.4.3 External Trigger Input Signals59027.4.4 Multiplexed Address Output Signals59027.4.5 Multiplexed Analog Input Signals590Table 27-1. Multiplexed Analog Input Channels59127.4.6 Voltage Reference Signals59127.4.7 Dedicated Analog Supply Signals59127.4.8 Dedicated Digital I/O Port Supply Signal59127.5 Memory Map591Table 27-2. QADC Memory Map59227.6 Register Descriptions59227.6.1 QADC Module Configuration Register (QADCMCR)592Figure 27-3. QADC Module Configuration Register (QADCMCR)593Table 27-3. QADCMCR Field Descriptions59327.6.2 QADC Test Register (QADCTEST)59327.6.3 Port Data Registers (PORTQA and PORTQB)593Figure 27-4. QADC Port QA Data Register (PORTQA)594Figure 27-5. QADC Port QB Data Register (PORTQB)59427.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)594Figure 27-6. QADC Port QA Data Direction Register (DDRQA)595Figure 27-7. Port QB Data Direction Register (DDRQB)59527.6.5 Control Registers59527.6.5.1 QADC Control Register 0 (QACR0)595Figure 27-8. QADC Control Register 0 (QACR0)596Table 27-4. QACR0 Field Descriptions596Table 27-5. Prescaler fSYS Divide-by Values59727.6.5.2 QADC Control Register 1 (QACR1)598Figure 27-9. QADC Control Register 1 (QACR1)598Table 27-6. QACR1 Field Descriptions598Table 27-7. Queue 1 Operating Modes59927.6.5.3 QADC Control Register 2 (QACR2)600Figure 27-10. QADC Control Register 2 (QACR2)601Table 27-8. QACR2 Field Descriptions602Table 27-9. Queue 2 Operating Modes (continued)60227.6.6 Status Registers60327.6.6.1 QADC Status Register 0 (QASR0)603Figure 27-11. QADC Status Register 0 (QASR0)606Table 27-10. QASR0 Field Descriptions607Table 27-11. CCW Pause Bit Response607Table 27-12. Queue Status608Figure 27-12. Queue Status Transition60927.6.6.2 QADC Status Register 1 (QASR1)610Figure 27-13. QADC Status Register 1 (QASR1)610Table 27-13. QASR1 Field Descriptions61027.6.7 Conversion Command Word Table (CCW)610Figure 27-14. Conversion Command Word Table (CCW)611Table 27-14. CCW Field Descriptions (continued)611Table 27-15. Input Sample Times612Table 27-16. Non-Multiplexed Channel Assignments and Signal Designations612Table 27-17. Multiplexed Channel Assignments and Signal Designations61327.6.8 Result Registers61327.6.8.1 Right-Justified Unsigned Result Register (RJURR)613Figure 27-15. Right-Justified Unsigned Result Register (RJURR)613Table 27-18. RJURR Field Descriptions61427.6.8.2 Left-Justified Signed Result Register (LJSRR)614Figure 27-16. Left-Justified Signed Result Register (LJSRR)614Table 27-19. LJSRR Field Descriptions61427.6.8.3 Left-Justified Unsigned Result Register (LJURR)614Figure 27-17. Left-Justified Unsigned Result Register (LJURR)615Table 27-20. LJURR Field Descriptions61527.7 Functional Description61527.7.1 Result Coherency61527.7.2 External Multiplexing61527.7.2.1 External Multiplexing Operation616Figure 27-18. External Multiplexing Configuration61727.7.2.2 Module Version Options618Table 27-21. Analog Input Channels61827.7.3 Analog Subsystem61827.7.3.1 Analog-to-Digital Converter Operation618Figure 27-19. QADC Analog Subsystem Block Diagram61927.7.3.2 Conversion Cycle Times619Figure 27-20. Conversion Timing620Figure 27-21. Bypass Mode Conversion Timing62027.7.3.3 Channel Decode and Multiplexer62027.7.3.4 Sample Buffer62027.7.3.5 Comparator62127.7.3.6 Bias62127.7.3.7 Successive Approximation Register (SAR)62127.7.3.8 State Machine62127.8 Digital Control Subsystem62127.8.1 Queue Priority Timing Examples62227.8.1.1 Queue Priority622Figure 27-22. QADC Queue Operation with Pause62327.8.1.2 Queue Priority Schemes624Table 27-22. Trigger Events624Table 27-23. Status Bits624Figure 27-23. CCW Priority Situation 1625Figure 27-24. CCW Priority Situation 2626Figure 27-25. CCW Priority Situation 3626Figure 27-26. CCW Priority Situation 4627Figure 27-27. CCW Priority Situation 5627Figure 27-28. CCW Priority Situation 6628Figure 27-29. CCW Priority Situation 7628Figure 27-30. CCW Priority Situation 8629Figure 27-31. CCW Priority Situation 9629Figure 27-32. CCW Priority Situation 10630Figure 27-33. CCW Priority Situation 11630Figure 27-34. CCW Freeze Situation 12631Figure 27-35. CCW Freeze Situation 13631Figure 27-36. CCW Freeze Situation 14631Figure 27-37. . CCW Freeze Situation 15631Figure 27-38. CCW Freeze Situation 16632Figure 27-39. CCW Freeze Situation 17632Figure 27-40. CCW Freeze Situation 18632Figure 27-41. CCW Freeze Situation 1963227.8.2 Boundary Conditions63327.8.3 Scan Modes63427.8.4 Disabled Mode63427.8.5 Reserved Mode63427.8.6 Single-Scan Modes63427.8.6.1 Software-Initiated Single-Scan Mode63527.8.6.2 Externally Triggered Single-Scan Mode63627.8.6.3 Externally Gated Single-Scan Mode63627.8.6.4 Interval Timer Single-Scan Mode63727.8.7 Continuous-Scan Modes63827.8.7.1 Software-Initiated Continuous-Scan Mode63927.8.7.2 Externally Triggered Continuous-Scan Mode64027.8.7.3 Externally Gated Continuous-Scan Mode64027.8.7.4 Periodic Timer Continuous-Scan Mode64127.8.8 QADC Clock (QCLK) Generation641Figure 27-42. QADC Clock Subsystem Functions64227.8.9 Periodic/Interval Timer64227.8.10 Conversion Command Word Table643Figure 27-43. QADC Conversion Queue Operation64427.8.11 Result Word Table64627.9 Signal Connection Considerations64627.9.1 Analog Reference Signals64727.9.2 Analog Power Signals647Figure 27-44. Equivalent Analog Input Circuitry647Figure 27-45. Errors Resulting from Clipping64827.9.3 Conversion Timing Schemes648Figure 27-46. External Positive Edge Trigger Mode Timing with Pause649Figure 27-47. Gated Mode, Single Scan Timing650Figure 27-48. Gated Mode, Continuous Scan Timing65127.9.4 Analog Supply Filtering and Grounding651Figure 27-49. Star-Ground at the Point of Power Supply Origin65227.9.5 Accommodating Positive/Negative Stress Conditions653Figure 27-50. Input Signal Subjected to Negative Stress653Figure 27-51. Input Signal Subjected to Positive Stress65427.9.6 Analog Input Considerations655Figure 27-52. External Multiplexing of Analog Signal Sources65627.9.7 Analog Input Pins657Figure 27-53. Electrical Model of an A/D Input Signal65727.9.7.1 Settling Time for the External Circuit658Table 27-24. External Circuit Settling Time to 1/2 LSB65827.9.7.2 Error Resulting from Leakage659Table 27-25. Error Resulting from Input Leakage (IOff)65927.10 Interrupts65927.10.1 Interrupt Operation659Table 27-26. QADC Status Flags and Interrupt Sources66027.10.2 Interrupt Sources660Chapter 28 Reset Controller Module66128.1 Features66128.2 Block Diagram662Figure 28-1. Reset Controller Block Diagram66228.3 Signals662Table 28-1. Reset Controller Signal Properties66228.3.1 RSTI66228.3.2 RSTO66228.4 Memory Map and Registers663Table 28-2. Reset Controller Memory Map66328.4.1 Reset Control Register (RCR)663Figure 28-2. Reset Control Register (RCR)663Table 28-3. RCR Field Descriptions (continued)66328.4.2 Reset Status Register (RSR)664Figure 28-3. Reset Status Register (RSR)664Table 28-4. RSR Field Descriptions66528.5 Functional Description66628.5.1 Reset Sources666Table 28-5. Reset Source Summary66628.5.1.1 Power-On Reset66628.5.1.2 External Reset66728.5.1.3 Watchdog Timer Reset66728.5.1.4 Loss-of-Clock Reset66728.5.1.5 Loss-of-Lock Reset66728.5.1.6 Software Reset66728.5.1.7 LVD Reset66728.5.2 Reset Control Flow668Figure 28-4. Reset Control Flow66928.5.2.1 Synchronous Reset Requests67028.5.2.2 Internal Reset Request67028.5.2.3 Power-On Reset/Low-Voltage Detect Reset67028.5.3 Concurrent Resets67028.5.3.1 Reset Flow67028.5.3.2 Reset Status Flags671Chapter 29 Debug Support67329.1 Overview673Figure 29-1. Processor/Debug Module Interface67329.2 Signal Description674Table 29-1. Debug Module Signals674Figure 29-2. CLKOUT Timing67429.3 Real-Time Trace Support675Table 29-2. Processor Status Encoding (continued)67529.3.1 Begin Execution of Taken Branch (PST = 0x5)676Figure 29-3. Example JMP Instruction Output on PST/DDATA67729.4 Programming Model677Figure 29-4. Debug Programming Model678Table 29-3. BDM/Breakpoint Registers67929.4.1 Revision A Shared Debug Resources679Table 29-4. Rev. A Shared BDM/Breakpoint Hardware67929.4.2 Address Attribute Trigger Register (AATR)680Figure 29-5. Address Attribute Trigger Register (AATR)680Table 29-5. AATR Field Descriptions (continued)68029.4.3 Address Breakpoint Registers (ABLR, ABHR)681Figure 29-6. Address Breakpoint Registers (ABLR, ABHR)681Table 29-6. ABLR Field Description682Table 29-7. ABHR Field Description68229.4.4 Configuration/Status Register (CSR)682Figure 29-7. Configuration/Status Register (CSR)682Table 29-8. CSR Field Descriptions (continued)68329.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)684Figure 29-8. Data Breakpoint/Mask Registers (DBR/DBMR)684Table 29-9. DBR Field Descriptions685Table 29-10. DBMR Field Descriptions685Table 29-11. Access Size and Operand Data Location68529.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)685Figure 29-9. Program Counter Breakpoint Register (PBR)686Table 29-12. PBR Field Descriptions686Figure 29-10. Program Counter Breakpoint Mask Register (PBMR)686Table 29-13. PBMR Field Descriptions68629.4.7 Trigger Definition Register (TDR)686Figure 29-11. Trigger Definition Register (TDR)687Table 29-14. TDR Field Descriptions (continued)68729.5 Background Debug Mode (BDM)68829.5.1 CPU Halt68829.5.2 BDM Serial Interface690Figure 29-12. BDM Serial Interface Timing69029.5.2.1 Receive Packet Format691Figure 29-13. Receive BDM Packet691Table 29-15. Receive BDM Packet Field Description69129.5.2.2 Transmit Packet Format691Figure 29-14. Transmit BDM Packet691Table 29-16. Transmit BDM Packet Field Description69129.5.3 BDM Command Set692Table 29-17. BDM Command Summary69229.5.3.1 ColdFire BDM Command Format693Figure 29-15. BDM Command Format693Table 29-18. BDM Field Descriptions69329.5.3.2 Command Sequence Diagrams694Figure 29-16. Command Sequence Diagram69429.5.3.3 Command Set Descriptions695Figure 29-17. rareg/rdreg Command Format695Figure 29-18. rareg/rdreg Command Sequence695Figure 29-19. wareg/wdreg Command Format696Figure 29-20. wareg/wdreg Command Sequence696Figure 29-21. read Command/Result Formats697Figure 29-22. read Command Sequence697Figure 29-23. write Command Format698Figure 29-24. write Command Sequence699Figure 29-25. dump Command/Result Formats700Figure 29-26. dump Command Sequence701Figure 29-27. fill Command Format702Figure 29-28. fill Command Sequence702Figure 29-29. go Command Format703Figure 29-30. go Command Sequence703Figure 29-31. nop Command Format703Figure 29-32. nop Command Sequence703Figure 29-33. rcreg Command/Result Formats704Table 29-19. Control Register Map704Figure 29-34. rcreg Command Sequence705Figure 29-35. wcreg Command/Result Formats706Figure 29-36. wcreg Command Sequence707Figure 29-37. rdmreg Command/Result Formats707Table 29-20. Definition of DRc Encoding-Read708Figure 29-38. rdmreg Command Sequence708Figure 29-39. wdmreg BDM Command Format708Figure 29-40. wdmreg Command Sequence70829.6 Real-Time Debug Support70929.6.1 Theory of Operation709Table 29-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response70929.6.1.1 Emulator Mode71029.6.2 Concurrent BDM and Processor Operation71129.7 Processor Status, DDATA Definition71229.7.1 User Instruction Set712Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued)712Table 29-23. PST/DDATA Specification for MAC Instructions (continued)71529.7.2 Supervisor Instruction Set716Table 29-24. PST/DDATA Specification for Supervisor-Mode Instructions71629.8 Motorola-Recommended BDM Pinout717Figure 29-41. Recommended BDM Connector717Chapter 30 Chip Configuration Module (CCM)71930.1 Features71930.2 Modes of Operation71930.2.1 Master Mode72030.2.2 Single-Chip Mode72030.3 Block Diagram720Figure 30-1. Chip Configuration Module Block Diagram72030.4 Signal Descriptions721Table 30-1. Signal Properties72130.4.1 RCON72130.4.2 CLKMOD[1:0]72130.4.3 D[26:24, 21, 19:16] (Reset Configuration Override)72130.5 Memory Map and Registers72130.5.1 Programming Model721Table 30-2. Write-Once Bits Read/Write Accessibility72230.5.2 Memory Map722Table 30-3. Chip Configuration Module Memory Map72230.5.3 Register Descriptions72330.5.3.1 Chip Configuration Register (CCR)723Figure 30-2. Chip Configuration Register (CCR)723Table 30-4. CCR Field Descriptions (continued)72330.5.3.2 Reset Configuration Register (RCON)724Figure 30-3. Reset Configuration Register (RCON)724Table 30-5. RCON Field Descriptions (continued)724Table 30-6. RCSC Chip Select Configuration725Table 30-7. BOOTPS Port Size Configuration72530.5.3.3 Chip Identification Register (CIR)726Figure 30-4. Chip Identification Register (CIR)726Table 30-8. CIR Field Description72630.6 Functional Description72630.6.1 Reset Configuration726Table 30-9. Reset Configuration Pin States During Reset727Table 30-10. Configuration During Reset (continued)72730.6.2 Chip Mode Selection728Table 30-11. Chip Configuration Mode Selection72930.6.3 Boot Device Selection72930.6.4 Output Pad Strength Configuration729Table 30-12. Output Pad Driver Strength Selection72930.6.5 Clock Mode Selection729Table 30-13. Clock Mode Selection73030.6.6 Chip Select Configuration73030.7 Reset73030.8 Interrupts730Chapter 31 IEEE 1149.1 Test Access Port (JTAG)731Figure 31-1. JTAG Block Diagram73231.1 Features73231.2 Modes of Operation73331.3 External Signal Description73331.3.1 Detailed Signal Description733Table 31-1. Signal Properties73331.3.1.1 JTAG_EN - JTAG Enable733Table 31-2. Pin Function Selected733Table 31-3. Signal State to the Disable Module73431.3.1.2 TCLK - Test Clock Input73431.3.1.3 TMS/BKPT - Test Mode Select / Breakpoint73431.3.1.4 TDI/DSI - Test Data Input / Development Serial Input73431.3.1.5 TRST/DSCLK - Test Reset / Development Serial Clock73431.3.1.6 TDO/DSO - Test Data Output / Development Serial Output73531.4 Memory Map/Register Definition73531.4.1 Memory Map73531.4.2 Register Descriptions73531.4.2.1 Instruction Shift Register (IR)73531.4.2.2 IDCODE Register735Figure 31-2. IDCODE Register735Table 31-4. IDCODE Register Field Descriptions73631.4.2.3 Bypass Register73631.4.2.4 JTAG_CFM_CLKDIV Register73631.4.2.5 TEST_CTRL Register73631.4.2.6 Boundary Scan Register73631.5 Functional Description73731.5.1 JTAG Module73731.5.2 TAP Controller737Figure 31-3. TAP Controller State Machine Flow73831.5.3 JTAG Instructions738Table 31-5. JTAG Instructions (continued)73831.5.3.1 External Test Instruction (EXTEST)73931.5.3.2 IDCODE Instruction73931.5.3.3 SAMPLE/PRELOAD Instruction73931.5.3.4 TEST_LEAKAGE Instruction74031.5.3.5 ENABLE_TEST_CTRL Instruction74031.5.3.6 HIGHZ Instruction74031.5.3.7 LOCKOUT_RECOVERY Instruction74031.5.3.8 CLAMP Instruction74131.5.3.9 BYPASS Instruction74131.6 Initialization/Application Information74131.6.1 Restrictions74131.6.2 Nonscan Chain Operation742Chapter 32 Mechanical Data74332.1 Pinout744Figure 32-1. MCF5282 Pinout (256 MAPBGA)744Table 32-1. MCF5282 Signal Description by Pin Number (Continued)745Figure 32-2. 256 MAPBGA Package Dimensions74932.2 Ordering Information749Table 32-2. Orderable Part Numbers749Chapter 33 Electrical Characteristics75133.1 Maximum Ratings751Table 33-1. Absolute Maximum Ratings, (Continued)75133.2 Thermal Characteristics753Table 33-2. Thermal Characteristics75333.3 DC Electrical Specifications754Table 33-3. DC Electrical Specifications (Continued)75433.4 Phase Lock Loop Electrical Specifications756Table 33-4. PLL Electrical Specifications75633.5 QADC Electrical Characteristics757Table 33-5. QADC Absolute Maximum Ratings757Table 33-6. QADC Electrical Specifications (Operating) (Continued)757Table 33-7. QADC Conversion Specifications (Operating)75933.6 Flash Memory Characteristics759Table 33-8. SGFM Flash Program and Erase Characteristics759Table 33-9. SGFM Flash Module Life Characteristics76033.7 External Interface Timing Characteristics760Table 33-10. Processor Bus Input Timing Specifications760Figure 33-1. General Input Timing Requirements76133.8 Processor Bus Output Timing Specifications761Table 33-11. External Bus Output Timing Specifications (Continued)761Figure 33-2. Read/Write (Internally Terminated) Timing763Figure 33-3. Read Bus Cycle Terminated by TA764Figure 33-4. Read Bus Cycle Terminated by TEA765Figure 33-5. SDRAM Read Cycle766Table 33-12. SDRAM Timing766Figure 33-6. SDRAM Write Cycle76733.9 General Purpose I/O Timing767Table 33-13. GPIO Timing, (Continued)767(VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V)767Figure 33-7. GPIO Timing76833.10 Reset and Configuration Override Timing768Table 33-14. Reset and Configuration Override Timing (Continued)768Figure 33-8. RSTI and Configuration Override Timing76933.11 I2C Input/Output Timing Specifications769Table 33-15. I2C Input Timing Specifications between SCL and SDA769Table 33-16. I2C Output Timing Specifications between SCL and SDA770Figure 33-9. I2C Input/Output Timings77033.12 Fast Ethernet AC Timing Specifications77033.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)771Table 33-17. MII Receive Signal Timing771Figure 33-10. MII Receive Signal Timing Diagram77133.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)771Table 33-18. MII Transmit Signal Timing772Figure 33-11. MII Transmit Signal Timing Diagram77233.12.3 MII Async Inputs Signal Timing (ECRS and ECOL)772Table 33-19. MII Async Inputs Signal Timing772Figure 33-12. MII Async Inputs Timing Diagram77233.12.4 MII Serial Management Channel Timing (EMDIO and EMDC)773Table 33-20. MII Serial Management Channel Timing773Figure 33-13. MII Serial Management Channel Timing Diagram77333.13 DMA Timer Module AC Timing Specifications774Table 33-21. Timer Module AC Timing Specifications77433.14 QSPI Electrical Specifications774Table 33-22. QSPI Modules AC Timing Specifications774Figure 33-14. QSPI Timing77433.15 JTAG and Boundary Scan Timing775Table 33-23. JTAG and Boundary Scan Timing775Figure 33-15. Test Clock Input Timing775Figure 33-16. Boundary Scan (JTAG) Timing776Figure 33-17. Test Access Port Timing776Figure 33-18. TRST Timing776Figure 33-19. BKPT Timing77733.16 Debug AC Timing Specifications777Table 33-24. Debug AC Timing Specification777Figure 33-20. Real-Time Trace AC Timing778Figure 33-21. BDM Serial Port AC Timing778Appendix A Register Memory Map779Table A-1. CPU Space Register Memory Map779Table A-2. Module Memory Map Overview780Table A-3. Register Memory Map (Continued)781サイズ: 9.4MBページ数: 816Language: Englishマニュアルを開く