Motorola MCF5281 ユーザーズマニュアル
8-16
MCF5282 User’s Manual
MOTOROLA
System Access Control Unit (SACU)
8.6.3.1
Master Privilege Register (MPR)
The MPR specifies the access privilege level associated with each bus master in the
platform. The register provides one bit per bus master, where bit 3 corresponds to master 3
(Fast Ethernet Controller), bit 2 to master 2 (DMA Controller), bit1 to master 1 (internal
bus master), and bit 0 to master 0 (ColdFire core).
platform. The register provides one bit per bus master, where bit 3 corresponds to master 3
(Fast Ethernet Controller), bit 2 to master 2 (DMA Controller), bit1 to master 1 (internal
bus master), and bit 0 to master 0 (ColdFire core).
Only trusted bus masters can modify the access control registers. If a non-trusted bus master
attempts to write any of the SACU control registers, the access is aborted with an error
termination and the registers remain unaffected.
attempts to write any of the SACU control registers, the access is aborted with an error
termination and the registers remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus
master. Accordingly, MPR[0] is forced to 1 at reset.
master. Accordingly, MPR[0] is forced to 1 at reset.
8.6.3.2
Peripheral Access Control Registers (PACR 0–PACR8)
Access to several on-chip peripherals is controlled by shared peripheral access control
registers. A single PACR defines the access level for each of the two modules. These
registers. A single PACR defines the access level for each of the two modules. These
0x028
PACR4
—
PACR5
PACR6
0x02c
PACR7
—
PACR8
—
0x030
GPACR0
GPACR1
—
—
0x034
—
—
—
—
0x038
—
—
—
—
0x03C
—
—
—
—
7
0
Field
—
MPR[3:0]
Reset
0000_0011
R/W
R/W
Address
IPSBAR + 0x020
Figure 8-8. Master Privilege Register (MPR)
Table 8-9. MPR[n] Field Descriptions
Bits Name
Description
7–4
—
Reserved. Should be cleared.
3–0
MPR
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
Table 8-8. SACU Register Memory Map (continued)
IPSBAR
Offset
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]