Motorola MCF5281 ユーザーズマニュアル

9-2

MOTOROLA

 

In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input
reference frequency. The post divider is not active.

In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL.
The resulting operating frequency is equal to the external clock frequency.

This subsection describes the operation of the clock module in low-power and halted modes
of operation. Low-power modes are described in Chapter 7, “Power Management.”
Table 9-1 shows the clock module operation in low-power modes.

During wakeup from a low-power mode, the Flash clock always clocks through at least 16
cycles before the CPU clocks are enabled. This allows the Flash module time to recover
from the low-power mode, and software can immediately resume fetching instructions
from memory.

In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to
the CPU, Flash, and SRAM are stopped. Each module can disable its clock locally at the
module level.

In stop mode, all system clocks are disabled. There are several options for enabling or
disabling the PLL or crystal oscillator in stop mode, compromising between stop mode
current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a
wakeup period before it can relock. The oscillator can also be disabled during stop mode,
but requires a wakeup period to restart.

When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can
support systems using CLKOUT as the clock source.

Wait

Clocks sent to peripheral modules only

Exit not caused by clock module, but normal 

clocking resumes upon mode exit

Doze

Clocks sent to peripheral modules only

Exit not caused by clock module, but normal 

clocking resumes upon mode exit

Stop

All system clocks disabled

Exit not caused by clock module, but clock 

sources are re-enabled and normal clocking 

resumes upon mode exit

Halted

Normal

Exit not caused by clock module