Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 15. Synchronous DRAM Controller Module
15-3
SDRAM Controller Operation
• Address multiplexing—Multiplexes addresses to allow column and row addresses
to share pins. This allows glueless interface to SDRAMs.
• Data Generation—Controls the data input and data output transmission between the
on-platform and off-platform data buses.
15.2 SDRAM Controller Operation
By running synchronously with the system clock, SDRAM can (after an initial latency
period) be accessed on every clock; 5-1-1-1 is a typical MCF5282 burst rate to the
SDRAM. Unlike the MCF5272, the MCF5282 does not have an independent SDRAM
clock signal. For the MCF5282, the timing of the SDRAM controller is controlled by the
CLKOUT signal.
period) be accessed on every clock; 5-1-1-1 is a typical MCF5282 burst rate to the
SDRAM. Unlike the MCF5272, the MCF5282 does not have an independent SDRAM
clock signal. For the MCF5282, the timing of the SDRAM controller is controlled by the
CLKOUT signal.
Note that because the MCF5282 cannot have more than one page open at a time, it does not
support interleaving.
support interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not
only must they manage addresses and data, but they must send special commands for such
functions as precharge, read, write, burst, auto-refresh, and various combinations of these
functions. Table 15-1 lists common SDRAM commands.
only must they manage addresses and data, but they must send special commands for such
functions as precharge, read, write, burst, auto-refresh, and various combinations of these
functions. Table 15-1 lists common SDRAM commands.
SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data
pipelines and commands to initiate special actions. Commands are issued to memory using
specific encodings on address and control pins. Soon after system reset, a command must
be sent to the SDRAM mode register to configure SDRAM operating parameters.
pipelines and commands to initiate special actions. Commands are issued to memory using
specific encodings on address and control pins. Soon after system reset, a command must
be sent to the SDRAM mode register to configure SDRAM operating parameters.
Table 15-1. SDRAM Commands
Command
Definition
ACTV
Activate. Executed before
READ
or
WRITE
executes; SDRAM registers and decodes row address.
MRS
Mode register set.
NOP
No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; SRAS asserted.
PALL
Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened.
READ
Read access. SDRAM registers column address and decodes that a read access is occurring.
REF
Refresh. Refreshes internal bank rows of an SDRAM component.
SELF
Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
SELFX
Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
WRITE
Write access. SDRAM registers column address and decodes that a write access is occurring.