Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
22-3
Operation
22.3.2 Internal Bus Interface
Because the QSPI module only operates in master mode, the master bit in the QSPI mode
register, QMR[MSTR], must be set for the QSPI to function properly. The QSPI can initiate
serial transfers but cannot respond to transfers initiated by other QSPI masters.
register, QMR[MSTR], must be set for the QSPI to function properly. The QSPI can initiate
serial transfers but cannot respond to transfers initiated by other QSPI masters.
22.4 Operation
The QSPI uses a dedicated 80-Byte block of static RAM accessible both to the module and
the CPU to perform queued operations. The RAM is divided into three segments as follows:
the CPU to perform queued operations. The RAM is divided into three segments as follows:
• 16 command control bytes (command RAM)
• 16 transmit data words (transfer RAM)
• 16 receive data words (transfer RAM)
• 16 transmit data words (transfer RAM)
• 16 receive data words (transfer RAM)
The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and
1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).
1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).
NOTE
Throughout ColdFire documentation, “word” is used
consistently and exclusively to designate a 16-bit data unit. The
only exceptions to this appear in discussions of serial
communication modules such as QSPI that support
variable-length data units. To simplify these discussions the
functional unit is referred to as a ‘word’ regardless of length.
consistently and exclusively to designate a 16-bit data unit. The
only exceptions to this appear in discussions of serial
communication modules such as QSPI that support
variable-length data units. To simplify these discussions the
functional unit is referred to as a ‘word’ regardless of length.
The user initiates QSPI operation by loading a queue of commands in command RAM,
writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The
QSPI executes the queued commands and sets the completion flag in the QSPI interrupt
register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be
enabled to generate an interrupt.
writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The
QSPI executes the queued commands and sets the completion flag in the QSPI interrupt
register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be
enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in
QSPI wrap register (QWR):
QSPI wrap register (QWR):
• The new queue pointer, QWR[NEWQP], points to the first command in the queue.
• An internal queue pointer points to the command currently being executed.
• An internal queue pointer points to the command currently being executed.
Table 22-1. QSPI Input and Output Signals and Functions
Signal Name
Hi-Z or Actively Driven
Function
QSPI Data Output (QSPI_Dout)
Configurable
Serial data output from QSPI
QSPI Data Input (QSPI_Din)
N/A
Serial data input to QSPI
Serial Clock (QSPI_CLK)
Actively driven
Clock output from QSPI
Peripheral Chip Selects (QSPI_CS[3:0])
Actively driven
Peripheral selects