Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 25. FlexCAN
25-21
Programmer’s Model
Table 25-8. CANMCR Field Descriptions
Bits
Name
Description
15
STOP
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared either
by the CPU or by the FlexCAN, if the SELFWAKE bit is set.
0 Enable FlexCAN clocks
1 Disable FlexCAN clocks
by the CPU or by the FlexCAN, if the SELFWAKE bit is set.
0 Enable FlexCAN clocks
1 Disable FlexCAN clocks
14
FRZ
FREEZE assertion response. When FRZ = 1, the FlexCAN can enter debug mode when the BKPT
line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug
mode. Refer to Section 25.4.11.1, “Debug Mode” for more information.
0 FlexCAN ignores the BKPT signal and the HALT bit in the module configuration register.
1 FlexCAN module enabled to enter debug mode.
line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug
mode. Refer to Section 25.4.11.1, “Debug Mode” for more information.
0 FlexCAN ignores the BKPT signal and the HALT bit in the module configuration register.
1 FlexCAN module enabled to enter debug mode.
13
—
Reserved
12
HALT
Halt FlexCAN S-Clock. Setting the HALT bit has the same effect as assertion of the BKPT signal
on the FlexCAN without requiring that BKPT be asserted. This bit is set to one after reset. It should
be cleared after initializing the message buffers and control registers. FlexCAN message buffer
receive and transmit functions are inactive until this bit is cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is allowed.
0 The FlexCAN operates normally
1 FlexCAN enters debug mode if FRZ = 1
on the FlexCAN without requiring that BKPT be asserted. This bit is set to one after reset. It should
be cleared after initializing the message buffers and control registers. FlexCAN message buffer
receive and transmit functions are inactive until this bit is cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is allowed.
0 The FlexCAN operates normally
1 FlexCAN enters debug mode if FRZ = 1
11
NOTRDY
FlexCAN not ready. This bit indicates that the FlexCAN is either in low-power stop mode or debug
mode. This bit is read-only and is set only when the FlexCAN enters low-power stop mode or
debug mode. It is cleared once the FlexCAN exits either mode, either by synchronization to the
CAN bus or by the self-wake mechanism.
0 FlexCAN has exited low-power stop mode or debug mode.
1 FlexCAN is in low-power stop mode or debug mode.
mode. This bit is read-only and is set only when the FlexCAN enters low-power stop mode or
debug mode. It is cleared once the FlexCAN exits either mode, either by synchronization to the
CAN bus or by the self-wake mechanism.
0 FlexCAN has exited low-power stop mode or debug mode.
1 FlexCAN is in low-power stop mode or debug mode.
10
WAKEMSK
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 Wake up interrupt is disabled.
1 Wake up interrupt is enabled.
0 Wake up interrupt is disabled.
1 Wake up interrupt is enabled.
9
SOFTRST
Soft reset. When this bit is asserted, the FlexCAN resets its internal state machines (sequencer,
error counters, error flags, and timer) and the host interface registers (CANMCR, CANICR,
CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed (CAN-
CTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not changed.
This allows SOFTRST to be used as a debug feature while the system is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal FlexCAN circuitry
to completely reset before executing another access to CANMCR.
The FlexCAN clears this bit once the internal reset cycle is completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
error counters, error flags, and timer) and the host interface registers (CANMCR, CANICR,
CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed (CAN-
CTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not changed.
This allows SOFTRST to be used as a debug feature while the system is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal FlexCAN circuitry
to completely reset before executing another access to CANMCR.
The FlexCAN clears this bit once the internal reset cycle is completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
8
FRZACK
FlexCAN disable. When the FlexCAN enters debug mode, it sets the FRZACK bit. This bit should
be polled to determine if the FlexCAN has entered debug mode. When debug mode is exited, this
bit is negated once the FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited debug mode and the prescaler is enabled.
1 The FlexCAN has entered debug mode, and the prescaler is disabled.
be polled to determine if the FlexCAN has entered debug mode. When debug mode is exited, this
bit is negated once the FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited debug mode and the prescaler is enabled.
1 The FlexCAN has entered debug mode, and the prescaler is disabled.