Motorola MCF5281 ユーザーズマニュアル

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MOTOROLA

 

The MCF5282 supports circuit board test strategies based on the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test
access port (TAP) consisting of a 16-state controller, an instruction register, and three test
registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register).
The boundary scan register links the device’s pins into one shift register. Test logic,
implemented using static logic design, is independent of the device system logic.

The MCF5282 implementation supports the following:

• Perform boundary-scan operations to test circuit board electrical continuity
• Sample

 

MCF5282

 

system

 

pins

 

during

 

operation and transparently shift out the result

 

in the boundary scan register

• Bypass the MCF5282 for a given circuit board test by effectively reducing the

 

boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels

The MCF5282 contains three full-duplex UARTs that function independently. The three
UARTs can be clocked by the system clock, eliminating the need for an external crystal.

Each UART has the following features:

• Each can be clocked by the system clock, eliminating a need for an external UART 

clock

• Full-duplex asynchronous/synchronous receiver/transmitter channel
• Quadruple-buffered receiver
• Double-buffered transmitter
• Independently programmable receiver and transmitter clock sources
• Programmable data format:

— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits

• Each channel programmable to normal (full-duplex), automatic echo, local 

loop-back, or remote loop-back mode

• Automatic wake-up mode for multidrop applications
• Four maskable interrupt conditions
• All three UARTs have DMA request capability