Motorola MCF5281 ユーザーズマニュアル

MOTOROLA

Chapter 31.  IEEE 1149.1 Test Access Port (JTAG)  

31-5

The TDO pin is the LSB-first data output. Data is clocked out of TDO on the falling edge
of TCLK. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller
states.

The DSO pin provides serial output data in BDM mode. 

The JTAG module registers are not memory mapped and are only accessible through the
TDO/DSO pin.

All registers are shift-in and parallel load.

The JTAG module uses a 4-bit shift register with no parity. The IR transfers its value to a
parallel hold register and applies an instruction on the falling edge of TCLK when the TAP
state machine is in the update-IR state. To load an instruction into the shift portion of the
IR, place the serial data on the TDI pin before each rising edge of TCLK. The MSB of the
IR is the bit closest to the TDI pin, and the LSB is the bit closest to the TDO pin.

The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 31.5.3.2, “IDCODE Instruction.”

 

31

28

27

22

21

16

Field

PRN[[3:0]

DC[5:0]

PIN[9:0]

Reset PRN[3] PRN[2] PRN[1] PRN[0]

0111_01

PIN[9] PIN[8] PIN[7] PIN[6] PIN[5] PIN[4]

R/W

Read only

15

12

11

1

0

Field

PIN[9:0]

JEDEC[10]

ID

Reset

0000_0000_0000_0000

R/W

Read only