Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 2. ColdFire Core
2-5
Processor Register Description
2.2.2 EMAC Programming Model
The registers in the EMAC portion of the user programming model, are described in
Section Chapter 5, “Enhanced Multiply-Accumulate Unit (EMAC),” and include the
following registers:
Section Chapter 5, “Enhanced Multiply-Accumulate Unit (EMAC),” and include the
following registers:
• Four 48-bit accumulator registers partitioned as follows:
— Four 32-bit accumulators (ACC0–ACC3)
— Eight 8-bit accumulator extension bytes (two per accumulator). These are
— Eight 8-bit accumulator extension bytes (two per accumulator). These are
grouped into two 32-bit values for load and store operations (ACCEXT01 and
ACCEXT23).
ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results
from EMAC arithmetic operations generally affect the entire 48-bit destination.
from EMAC arithmetic operations generally affect the entire 48-bit destination.
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit
values for load and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit status register (MACSR) including four indicator bits signaling product
• One 32-bit status register (MACSR) including four indicator bits signaling product
or accumulation overflow (one for each accumulator: PAV0–PAV3)
Figure 2-4. EMAC Register Set
2.2.3
Supervisor Programming Model
Only system control software is intended to use the supervisor programming model to
implement restricted operating system functions, I/O control, and memory management.
All accesses that affect the control features of ColdFire processors are in the supervisor
programming model, which consists of registers available in user mode as well as the
following control registers:
implement restricted operating system functions, I/O control, and memory management.
All accesses that affect the control features of ColdFire processors are in the supervisor
programming model, which consists of registers available in user mode as well as the
following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
31
0
MACSR
MAC status register
ACC0
MAC accumulator 0
ACC1
MAC accumulator 1
ACC2
MAC accumulator 2
ACC3
MAC accumulator 3
ACCext01 Extensions for ACC0 and ACC1
ACCext23 Extensions for ACC2 and ACC3
MASK
ACCext23 Extensions for ACC2 and ACC3
MASK
MAC mask register