Motorola MCF5281 ユーザーズマニュアル
MOTOROLA
Chapter 2. ColdFire Core
2-17
Processor Exceptions
The reset exception places the processor in the supervisor mode by setting the S-bit and
disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets
the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the
VBR is initialized to zero (0x00000000). The control registers specifying the operation of
any memories (e.g., cache and/or RAM modules) connected directly to the processor are
disabled.
disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets
the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the
VBR is initialized to zero (0x00000000). The control registers specifying the operation of
any memories (e.g., cache and/or RAM modules) connected directly to the processor are
disabled.
NOTE
Other implementation-specific supervisor registers are also
affected. Refer to each of the modules in this user’s manual for
details on these registers.
affected. Refer to each of the modules in this user’s manual for
details on these registers.
Once the processor is granted the bus, it then performs two longword read bus cycles. The
first longword at address 0 is loaded into the stack pointer and the second longword at
address 4 is loaded into the program counter. After the initial instruction is fetched from
memory, program execution begins at the address in the PC. If an access error or address
error occurs before the first instruction is executed, the processor enters the fault-on-fault
halted state.
first longword at address 0 is loaded into the stack pointer and the second longword at
address 4 is loaded into the program counter. After the initial instruction is fetched from
memory, program execution begins at the address in the PC. If an access error or address
error occurs before the first instruction is executed, the processor enters the fault-on-fault
halted state.
ColdFire processors load hardware configuration information into the D0 and D1
general-purpose registers after system reset. The hardware configuration information is
loaded immediately after the reset-in signal is negated. This allows an emulator to read out
the contents of these registers via BDM to determine the hardware configuration.
general-purpose registers after system reset. The hardware configuration information is
loaded immediately after the reset-in signal is negated. This allows an emulator to read out
the contents of these registers via BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
Figure 2-8.
Figure 2-8.
31
24
23
20
19
16
Field
PF
VER
REV
Reset
1100_1111_0010_0000
R/W
R
15
14
13
12
11
10
8
7
4
3
0
Field
MAC DIV EMAC FPU MMU
—
ISA
DEBUG
Reset
0110_0000_1000_0000
R/W
R
Figure 2-8. D0 Hardware Configuration Info