Epson S1D13504 ユーザーズマニュアル
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Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
Note
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO
is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For
programming information, see S1D13504 Programming Notes and Examples, document number
X19A-G-002-xx.
when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO
is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For
programming information, see S1D13504 Programming Notes and Examples, document number
X19A-G-002-xx.
bit 7
EDO Read-Write Delay
This bit is used for EDO-DRAM to select the delay during the read-write transition. A “0” selects 2
MCLK delay for the read-write transition. A “1” selects 1 MCLK delay for the read-write DRAM.
This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transi-
tion. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz.
This bit is used for EDO-DRAM to select the delay during the read-write transition. A “0” selects 2
MCLK delay for the read-write transition. A “1” selects 1 MCLK delay for the read-write DRAM.
This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transi-
tion. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz.
bits 6-5
RC Timing Value (N
RC
) Bits [1:0]
These bits select the DRAM random-cycle timing parameter, t
RC
. These bits specify the number
(N
RC
) of MCLK periods (T
M
) used to create t
RC
. N
RC
should be chosen to meet t
RC
as well as
t
RAS
, the RAS pulse width. Use the following two formulae to calculate N
RC
then choose the larger
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N
RC
= Round-Up (t
RC
/T
M
)
N
RC
= Round-Up (t
RAS
/T
M
+ N
RP
)
if N
RP
= 1 or 2
= Round-Up (t
RAS
/T
M
+ 1.55)
if N
RP
= 1.5
The resulting t
RC
is related to N
RC
as follows:
t
RC
= (N
RC
) T
M
bit 4
RAS# to CAS# Delay (N
RCD
)
This bit selects the DRAM RAS# to CAS# delay parameter, t
RCD
. This bit specifies the number
(N
RCD
) of MCLK periods (T
M
) used to create t
RCD
. N
RCD
must be chosen to satisfy the RAS#
access time, t
RAC
. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N
RCD
= Round-Up((t
RAC
+ 5)/T
M
- 1)
if EDO and N
RP
= 1 or 2
= 2
if EDO and N
RP
= 1.5
= Round-Up(t
RAC
/T
M
- 1)
if FPM and N
RP
= 1 or 2
= Round-Up(t
RAC
/T
M
- 0.45)
if FPM and N
RP
= 1.5
Performance Enhancement Register 0
REG[22h]
RW
EDO Read-
Write Delay
Write Delay
RC Timing
Value Bit 1
Value Bit 1
RC Timing
Value Bit 0
Value Bit 0
RAS# to
CAS# Delay
CAS# Delay
RAS#
Precharge
Timing Bit 1
Precharge
Timing Bit 1
RAS#
Precharge
Timing Bit 0
Precharge
Timing Bit 0
n/a
Reserved
Table 8-11: Minimum Memory Timing Selection
REG[22h] Bits [6:5]
N
RC
Minimum Random Cycle
Width (
t
RC
)
00
5
5 T
M
01
4
4 T
M
10
3
3 T
M
11
Reserved
Reserved