Epson S1D13504 ユーザーズマニュアル
Page 110
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
bit 7
Display FIFO Disable
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen
is blanked). This allows the S1D13504 to be dedicated to service CPU to memory accesses. When
this bit = 0 the display FIFO is enabled.
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen
is blanked). This allows the S1D13504 to be dedicated to service CPU to memory accesses. When
this bit = 0 the display FIFO is enabled.
bits 4-0
Display FIFO Threshold Bits [4:0]
These bits should be set to a value of 10h upon initialization as this provides the best overall perfor-
mance for all display modes.
These bits should be set to a value of 10h upon initialization as this provides the best overall perfor-
mance for all display modes.
8.2.8 Look-Up Table Registers
The S1D13504 has three internal 16 position, 4-bit wide Look-Up Tables. The 4-bit value
programmed into each table position determines the color weighting of display data; the output gray
shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode.
programmed into each table position determines the color weighting of display data; the output gray
shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode.
These three 16 position Look-Up Tables can be arranged in many different configurations to accom-
modate all the gray shade / color display modes.
modate all the gray shade / color display modes.
bits 5-4
RGB Index Bits [1:0]
These bits are also used to provide access to the three internal Look-Up Tables (RGB).
These bits are also used to provide access to the three internal Look-Up Tables (RGB).
A write to this register with RGB Index bits = 00 selected will position the internal pointer to the
Red LUT. Each read/write access to the LUT data will increment the counter to point to the next
LUT in order (R to G to B to R...). A read/write access to the Blue LUT will also automatically
increment the LUT address by 1. This provides an efficient method for sequential writing of RGB
data.
Red LUT. Each read/write access to the LUT data will increment the counter to point to the next
LUT in order (R to G to B to R...). A read/write access to the Blue LUT will also automatically
increment the LUT address by 1. This provides an efficient method for sequential writing of RGB
data.
When the RGB Index bits = 01, 10, or 11, the internal pointer always points to the respective R, G,
or B LUT. A read/write access to the LUT data will increment the LUT address by 1.
or B LUT. A read/write access to the LUT data will increment the LUT address by 1.
Performance Enhancement Register 1
REG[23h]
Display FIFO
Disable
Disable
n/a
n/a
Display FIFO
Threshold
Bit 4
Threshold
Bit 4
Display FIFO
Threshold
Bit 3
Threshold
Bit 3
Display FIFO
Threshold
Bit 2
Threshold
Bit 2
Display FIFO
Threshold
Bit 1
Threshold
Bit 1
Display FIFO
Threshold
Bit 0
Threshold
Bit 0
Look-Up Table Address Register
REG[24h]
RW
n/a
n/a
RGB Index
Bit 1
Bit 1
RGB Index
Bit 0
Bit 0
LUT Address
Bit 3
Bit 3
LUT Address
Bit 2
Bit 2
LUT Address
Bit 1
Bit 1
LUT Address
Bit 0
Bit 0
Table 8-15: RGB Index Selection
RGB Index Bits [1:0]
Look-Up Table Access
Pointer Sequence
00
Auto-Increment R, G, B LUT
R[n], G[n], B[n], R[n+1], G[n+1] . . .
01
Auto-Increment Red LUT only
R[n], R[n+1], R[n+2] . . .
10
Auto-Increment Green LUT only
G[n], G[n+1], G[n+2] . . .
11
Auto-Increment Blue LUT only
B[n], B[n+1], B[n+2] . . .