Epson S1D13504 ユーザーズマニュアル

Page 12

Vancouver Design Center

S1D13504

Hardware Functional Specification

X19A-A-002-18

Issue Date: 01/01/30

• 16-bit DRAM interface:

• EDO-DRAM up to 40MHz data rate (80M bytes per second).

• FPM-DRAM up to 25MHz data rate (50M bytes per second).

• Memory size options:

• 512K bytes using one 256K

×

16 device.

• 2M bytes using one 1M

×

16 device.

• A configuration register can be programmed to enhance performance by tailoring the memory 

control output timing to the DRAM device.

• Supports the following interfaces:

• 8/16-bit Hitachi SH-3 bus interface.

• 16-bit interface to 16/32-bit Motorola MC68K microprocessors/microcontrollers.

• Philips MIPS PR31500 / PR31700.

• NEC  MIPS  V

R

4102.

• 8/16-bit generic interface bus.

• One-Stage write buffer for minimum wait-state CPU writes.

• Registers are memory-mapped; M/R# pin selects between memory and register address space.

• The complete 2M byte display buffer address space is directly and contiguously available 

through the 21-bit address bus.

• 4/8-bit monochrome or 4/8/16-bit color passive LCD interface for single-panel, single-drive 

displays.

• 8-bit monochrome or 8/16-bit color passive LCD interface for dual-panel, dual-drive displays.

• Direct support for 9/12-bit TFT, 18/24-bit TFT are supported up to 64K color depth (16-bit data).

• External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel 

data bus.

• Simultaneous display of CRT and 4/8-bit passive panel or 9-bit TFT panel:

• Normal mode for cases where LCD and CRT image sizes are identical.

• Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480-

line CRT.

• Even-Scan and interlace modes for simultaneous display of 480-line images on 240-line LCD 

and 480-line CRT.