Epson S1D13504 ユーザーズマニュアル
Page 14
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
3 Typical System Implementation Diagrams
Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM
Power
Management
S1D13504
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLK
I
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
SH-3
BUS
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
WAIT#
A[20:0]
CKIO
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
SU
SPE
N
D
#
WAIT#
RESET#
A21
CSn#
WE1#
LCDPWR
WE
#
A
[11:
0]
D[
15:
0]
R
AS#
1Mx16
LCA
S
#
U
C
AS#
M
A
[11:
0]
M
D
[15:
0]
WE
#
R
AS#
LCA
S
#
U
C
AS#
FPM/EDO-DRAM